F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles 3.3. Generating IP-XACT File
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

1.1.1. Reconfiguration Group

A reconfiguration group is a set of single or multiple PMA lanes (transceivers), with different RS-FEC options, from which you can dynamically reconfigure your design. Each reconfiguration group defines the base profile (Profile #0) and a list of secondary profiles (Profile #1, Profile #2 .. to Profile #32).

The Reconfiguration group options are defined with the notation of G-Y Reconfigurable, where:
  • Y is the total number of PMA lane count allocated for the reconfiguration group.
For example, 50G-1 Reconfigurable group setting indicates that a 50G fracture (st_x2) is selected with one PMA lane configured for this reconfiguration group. You can also select a portion of the 50G fracture that is a lower rate, such as a 25G fracture (st_x1) in your reconfiguration profiles under the Reconfiguration subset parameter.
With the 50G-1 Reconfigurable group setting, you can configure your reconfiguration profiles to any of the following settings to suit your application. For example:
  • You can select a 50G fracture (st_x2) with data rate of 53.125 Gbps for the Ethernet protocol.
  • You can select a 25G fracture (st_x1) with data rates of 25.78125 Gbps and 10.3125 Gbps for Ethernet protocol.
  • You can select a 25G fracture (st_x1) with data rates of 24.33024 Gbps, 10.1376 Gbps, 9.8304 Gbps, 4.9152 Gbps and 2.4576 Gbps for CPRI protocol.
For more information about the Reconfiguration subset parameter refer to Parameter Settings: Profile #N (N=0-32) Tab. For more information about the fracture types, refer to the F-Tile Architecture and PMA and FEC Direct PHY Intel FPGA IP User Guide.
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