F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 4/01/2024
Public
Document Table of Contents

2.5. TX and RX PMA Status Signals

The following table describes the TX and RX PMA status signals that are a part of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

Table 11.  TX PMA Status SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
fgt_tx_beacon[N-1:0] Asynchronous Input

1'b1: enable SATA beacon signal.

1'b0: disable SATA beacon signal.

tx_pll_locked[N-1:0] Asynchronous Output TX channel PLL locked signal for both FGT and FHT to reference clock within the PPM threshold status signal for fast/medium or slow PLL. 1’b1 = locked. 1’b0 = not locked.
Table 12.  RX PMA Status Signals
Signal Name Clocks Domain/Resets Direction Description
fgt_rx_signal_detect[N-1:0] Asynchronous Output FGT RX signal detect indicator.
fgt_rx_signal_detect_lfps[N-1:0] Asynchronous Output

Indicates SATA low frequency periodic signaling (LFPS) signal detection.

rx_is_lockedtoref[N-1:0] Asynchronous Output CDR lock status signal.
  • 1’b1 – CDR is frequency locked to reference clock within the PPM threshold.
  • 1’b0 – CDR is not frequency locked within the PPM threshold. Applicable to FGT PMA only

When lockedtodata stays high, the lockedtoref signal status is insignificant.

rx_is_lockedtodata[N-1:0] Asynchronous Output RX CDR data lock status signal.
  • 1’b0: CDR is not locked to data.
  • 1’b1: CDR is locked to data. Applicable to both FGT and FHT PMA.

When asserted, indicates that the CDR is in locked-to-data mode. When continuously asserted and does not switch between asserted and deasserted, you can confirm that the CDR is actually locked to data.

fgt_rx_set_locktoref[N-1:0] Asynchronous Input

1'b1: keep CDR in lock to reference mode.

1'b0: keep CDR in auto mode.

fgt_rx_cdr_freeze[N-1: 0] Asynchronous Input This port is used in GPON to freeze the CDR lock state during inactive time-slots.