F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 4/01/2024
Public
Document Table of Contents

2.1. Clock Signals

The following table describes the clock signals that are a part of the clock interface of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.
Table 7.  TX and RX Reference Clock and Clock Output Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description

rx_clkout_stream<x>

rx_clkout2_stream<x>

tx_clkout_stream<x>

tx_clkout2_stream<x>

N/A Output Output port enabled by default. You can select one of these ports, by selecting TX/RX clock options. These are per stream in F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP as interfaces in the system mode requires clock signals to be single bit per clock.

coreclkin

N/A Input Core clock that is usually driven by system pll div by 2 clock. All FPGA soft logic uses these clocks.
tx_pll_refclk_link_xcvr<n>_prof<j> N/A Input These clock ports are 1 bit. This is neither physical nor logical port. You connect this to <out_refclk_fgt<x>> port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP. This connection guides Quartus® Prime Pro Edition software to correctly configure the clock network.
rx_cdr_refclk_link_xcvr<n>_prof<j> N/A Input These clock ports are 1 bit. This is neither physical nor logical port. You connect this to <out_refclk_fgt<x>> port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP. This connection guides Quartus® Prime Pro Edition software to correctly configure the clock network.
system_pll_clk_link N/A Input This is virtual representation of system PLL output clock. This is neither physical nor logical port. You connect this to <out_systempll_clk_0> port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP. This connection guides Quartus® Prime Pro Edition software to correctly configure the clock network.
Note: Ports ending in _link must connect to the F-Tile Reference and System PLL Clocks Intel® FPGA IP. These ports cannot be simulated.