F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles 3.3. Generating IP-XACT File
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration

To successfully reconfigure your PMA channel during run time, you can reconfigure the soft CSR to change the fracture settings from one reconfiguration subset mode to another.

Updating the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP reconfiguration soft CSR registers is part of the dynamic reconfiguration flow and is highlighted in step 3 below. Step 3 is required if you are changing the fracture settings. The registers that are being updated are the fracture count, PMA count per fracture, rate per PMA and FEC mode. Refer to F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core Reconfiguration Soft CSR Registers for details about the registers.

Note: The steps described below are applicable only when you are controlling the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP with the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP.
  1. Assert the tx_reset and rx_reset of the PMA channel that you want to reconfigure. Wait for tx_reset_ack and rx_reset_ack signal to assert.
  2. Write to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP control registers to disable the current profile, enable the target profile and trigger the start of dynamic reconfiguration process. Refer to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide for more information.
  3. If you are changing the fracture settings using the registers documented in F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core Reconfiguration Soft CSR Registers, write to the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP reconfiguration soft CSR registers to ensure that the PMA channel is set and updated correctly. Refer to Configuration Registers for the registers that you need to write and update. You only need to control the registers at offset address 0x820, 0x824 and 0x828, to change the fracture settings from one reconfiguration subset mode to another mode.
    For example, if you want to reconfigure the PMA lane to operate at 25.78125 Gbps (25G-1) with FEC disabled, you have to configure to the following address:
    • Write to 20’h820 with data 32’b00001_00001_0001.
    • Write to 20’h824 with data 32’h0.
    If you want to reconfigure one PMA lane to operate at 53.125 Gbps (50G-1) with FEC enabled (IEEE 802.3 RS(544,514) (CL 91,KP)), you have to configure to the following address:
    • Write to 20’h820 with data 32’b00001_00001_0010.
    • Write to 20’h824 with data 32’h2.
    If you are not updating the fracture settings, you can skip this step.
  4. Wait for the dynamic reconfiguration process to complete by reading the o_dr_new_cfg_applied status from the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP status register. Alternatively, you can check the o_dr_new_cfg_applied signal status from the F-Tile Dynamic Reconfiguration Intel FPGA IP module. The assertion of this signal indicates that the targeted profile is dynamically reconfigured and updated. Refer to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide for more information.
  5. De-assert tx_reset and rx_reset signal for the PMA channel that is undergoing the dynamic reconfiguration process. Wait for tx_ready and rx_ready signals to be asserted. The PMA lane is now dynamically reconfigured to the new profile and target settings.
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