F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 2/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles 3.3. Generating IP-XACT File
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

1.1.5. Supported Reconfiguration Groups

This section specifies the supported reconfiguration groups for FGT PMA.

The Reconfiguration subset defines a portion of the fracture set within the Reconfiguration group. The available subsets such as 400G, 300G, 150G, 200G, 100G, 50G and 25G are the fracture types that you can select from F-tile. For more information about the fracture types, refer to F-Tile Architecture and PMA and FEC Direct PHY Intel FPGA IP User Guide.

Table 1.  Available Reconfiguration Groups for FGT PMA
Reconfiguration Group Reconfiguration Subset Fracture Count for each Reconfiguration Subset Maximum Number of Lanes Modulation System PLL Frequency (in MHz) 1 PMA Type
400G-8 Reconfigurable

400G-8

200G-8

200G-4

100G-4

100G-2

50G-2

50G-1

25G-1

1

1

2

2

4

4

8

8

 8 NRZ/PAM4 830.078125 FGT
300G-12 Reconfigurable

300G-12

150G-6

100G-4

50G-2

25G-1

1

2

3

6

12

12

 NRZ/PAM4 830.078125 FGT
150G-6 Reconfigurable

150G-6

50G-2

25G-1

1

3

6

 6 NRZ/PAM4 830.078125 FGT
200G-8 Reconfigurable

200G-8

100G-4

50G-2

25G-1

1

2

4

8

 8 NRZ/PAM4 830.078125 FGT
200G-4 Reconfigurable

200G-4

100G-4

100G-2

50G-2

50G-1

25G-1

1

1

2

2

4

4

 4 NRZ/PAM4 830.078125 FGT
100G-4 Reconfigurable

100G-4

50G-2

25G-1

1

2

4

 4 NRZ/PAM4 830.078125 FGT

100G-2 Reconfigurable

100G-2

50G-2

50G-1

25G-1

1

1

2

2

 2 NRZ/PAM4 830.078125 FGT

50G-2 Reconfigurable

50G-2

25G-1

1

2

 2 NRZ/PAM4 830.078125 FGT

50G-1 Reconfigurable

50G-1

25G-1

1

1

 1 NRZ/PAM4 830.078125 FGT

25G-1 Reconfigurable

25G-1

1

 1 NRZ/PAM4 830.078125 FGT
1 The System PLL frequency output value must be >= than all reconfiguration profiles PMA parallel cock frequency (PMA data rate/PMA width)
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