F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 12/04/2023
Document Table of Contents
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3.1. Design Features

Setting the Enable Active Video Protocol to AXIS-VVP gives two design variants:
  • HDMI 2.1 RX-TX Direct Retransmit without video frame buffer
    • Fixed 225 MHz for TX and RX video clock (vid_clk) for the direct retransmit of the design
    • HDMI TX can run at fixed clock with the video valid (vid_valid) toggling from the RX
    • Video in and out use the same clock check box in the HDMI TX core Advanced Configuration table is turned on
  • HDMI 2.1 TX-TX Retransmit Design with video frame buffer
    • Fixed 225 MHz for RX video clock
    • TX video clock running at a frequency relative to the actual pixel clock (pixel clock/pixel-in-parallel)
    • Video frame buffer between RX and TX truncates or repeats the frame for the asynchronous clocking between RX and TX

Both design variants currently only support FRL mode.