F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 12/04/2023
Public
Document Table of Contents

4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.12.04 23.4 19.7.3
  • Added TMDS and DSC Passthrough modes.
  • Added a note about no support for design example simulation when Include I2C is selected in design example parameters.
2023.10.02 23.3 19.7.2
  • Updated the device OPN in the HDMI Intel FPGA IP Design Example Parameters section.
  • Updated all mentions of "F-tile" to "F-Tile" to align with marketing and the web pages.
2023.06.26 23.2 19.7.2 Updated the Design Parameters of the HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) section to include TMDS only selection for HDMI 2.1 variant.
2023.04.28 23.1 19.7.2 Added a new topic, Design Limitation (AXI/CV).
2023.04.03 23.1 19.7.2
  • Updated the following diagrams:
    • HDMI 2.1 RX-TX Retransmit Block Diagram
    • HDMI 2.1 RX-only Block Diagram
    • HDMI 2.1 TX-only Block Diagram
    • HDMI RX Top Components
  • Updated the following tables:
    • Factory Switch Settings according to Design Example Variant
    • HDMI RX Direction under IP Parameters
    • HDMI TX Direction under IP Parameters
    • HDMI RX Direction under Design Parameters
    • HDMI TX Direction under Design Parameters
  • Updated product family name to "Intel Agilex® 7".
2022.12.27 22.4 19.7.1 Improved usability by updating platform designer interface for Enable Active Video Protocol = AXIS-VVP Full design example.
2022.10.14 22.3 19.7.1
  • Updated the design structure for HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full).
  • Updated the Platform Design System table in the Interface Signals section.
  • Removed the HDMI RX PHY and HDMI TX PHY tables, and RX-TX Link topic from the Interface Signals section of the HDMI 2.1 DE with AXI4-stream Interface Enabled section.
  • Updated the steps on how to support additional video resolutions in the Hardware Setup section.
2022.08.05 22.2 19.7.0
  • Added a section, HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full).
  • Updated Generated RTL Files table.
  • Updated step 8 in Generating the Design section.
  • Updated Compiling and Testing the Design section with additional design examples and updated the note in the final step.
  • Updated topic title HDMI 2.1 Design Example (Support FRL = 1) to HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None).
  • Updated HDMI TX Top Components figure.
  • Updated HDMI RX Top Components figure.
  • Updated the description of F-tile Reference and System PLL Clock module in Top-Level Common Blocks table.
  • Updated the clock frequency under Clock and Reset Signals of HDMI RX Top-Level Signals table.
  • Updated the clock frequency under Clock and Reset Signals of HDMI TX Top-Level Signals table.
  • Updated the F-tile Reference and System PLL Clock module in the Top-Level Common Blocks table to indicate that the configuration in the design example is only for HDMI application.
2022.04.22 22.1 19.7.0
  • Renamed the document title from HDMI Intel® Agilex™ F-Tile FPGA IP Design Example User Guide to F-Tile HDMI Intel FPGA IP Design Example User Guide.
  • Updated Directory Structure for the Design Example figure.
  • Updated Generated RTL Files table with additional folder and file/subfolders.li
  • Updated Generated Simulation Files table with additional folder and file/subfolders.
  • Updated default device in steps in Generating the Design section.
  • Added figure title Design Compilation and Hardware Flow in Compiling and Testing the Design section.
  • Added additional steps in Compiling and Testing the Design section.
  • Updated data rate in HDMI 2.1 Design Example for Intel Agilex F-tile Devices table.
  • Updated features in Design Features section.
  • Updated example, revision and version details in Hardware section in Hardware and Software Requirements section.
  • Updated HDMI 2.1 RX-TX Retransmit Block Diagram figure.
  • Updated HDMI 2.1 RX-only Block Diagram figure.
  • Updated HDMI 2.1 TX-only Block Diagram figure.
  • Updated Target Development Kit details in Design Example Parameters for Devices table.
  • Added Module details in HDMI TX Top Components table.
  • Updated clock signals for FRL in RX PHY Adapter section.
  • Updated clock signals for FRL in TX PHY Adaptersection.
  • Updated Top-Level Common Blocks table with addtional modules.
  • Updated RX Path Initialization Flowchart table.
  • Updated Clocking Scheme Signals table with additional clocks.
  • Added additional signals under On-board Oscillator Signal and User Push Buttons and LEDs in Top-Level Signals table.
  • Added additional signals under Clock and Reset Signals and RX Transceiver and IOPLL Signals in HDMI RX Top-Level Signals table.
  • Added a separate section for RX Reconfiguration Management and addtional signals in HDMI RX Top-Level Signals table.
  • Added additional signals under Clock and Reset Signals, TX Transceiver and IOPLL Signals, TX Reconfiguration Management and Hotplug Detect Signals in HDMI TX Top-Level Signals table.
  • Added additinal signals in RX-TX Link Signals table.
2021.12.13 21.4 19.6.1 Initial release.