F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 12/04/2023
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3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)

Figure 29. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer Block Diagram Clock Scheme