F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 12/04/2023
Public
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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-Tile Devices

Updated for:
Intel® Quartus® Prime Design Suite 23.4
IP Version 19.7.3
The HDMI Intel® FPGA IP design example for Intel Agilex® 7 F-Tile devices features a simulating testbench and a hardware design that supports compilation and hardware testing.
The HDMI Intel® FPGA IP offers the following design examples:
  • HDMI 2.1 Receiver-Transmitter (RX-TX) retransmit design with Fixed Rate Link (FRL) and Transition Minimized Differential Signaling (TMDS) mode on clocked video interface enabled
  • HDMI 2.1 Receiver-Transmitter (RX-TX) retransmit design with FRL mode on AXI4-stream (Full variant) interface with video frame buffer
  • HDMI 2.1 Receiver-Transmitter (RX-TX) retransmit design with FRL mode on AXI4-stream (Full variant) interface without video frame buffer
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Stages