F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

2.5.1.1.1. FRL and TMDS

In FRL and TMDS modes, HDMI TX core is running at 80 bits width. Since the TX PHY is configured to 64 bits width, you require an 80 bits to 128 bits converter and a mixed-width DCFIFO with 128 bits input and 64 bits output. In addition, in order to meet the inter-lane skew requirement, FRL data is oversampled twice. The TX PHY adapter comes with an oversample block to handle oversampling.

Figure 14. Block Diagram for the FRL Mode