F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 12/04/2023
Public
Document Table of Contents

3.6.7. Set TX Video Clock

Perform this step only if you are running the design with video frame buffer at the actual video clock. In this use case, a programmable oscillator supplies the video clock for HDMI TX with a frequency based on the following formula:

TX video clock = (actual pixel rate / pixels in parallel) * colour depth ratio

Table 26.  Color Depth Ratio

Color Depth

(Bit per Component)

Color Depth Ratio
8 1.00
10 1.25
12 1.50
16 2.00

Note that the design is running at 8 pixels in parallel.

The design example uses the TX video clock with the following resolution, color depth, and video clock frequency configurations. Expand this list according to your application.

Note: Both design variants currently only support 8bpc resolution. To add support for deep color resolution, refer to chapter 3.9.1 Supporting Additional Video Resolutions.
Table 27.  TX Video Clock based on Resolution and Color Depth
Resolution

Color Depth

(bit per component)

Pixel Rate

(MHz)

TX Video Clock

(MHz)

720x480p60 8 27 3.375
10 4.21875
12 5.0625
16 6.75
1280x720p60 8 74.25 9.28125
10 11.6015625
12 13.921875
16 18.5625
1920x1080p60 8 148.5 18.5625
10 23.203125
12 27.84375
16 37.125
3840x2160p60 8 594 74.25
10 92.8125
12 111.375
16 148.5
7680x4320p60 8 1188 148.5
10 185.625
12 222.75