F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 12/04/2023
Public
Document Table of Contents
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2.1. Design Features

The design example supports the following features:
  • HDMI configuration of:
    • 8 pixel-in-parallel in video domain (FRL)
    • 2 pixel-in-parallel in video domain (TMDS)
    • 8 symbols per clock in FRL domain
  • FRL and TMDS modes
  • Display Stream Compression (DSC) Passthrough mode (enabled by default when DSC source is detected)
  • EDID passthrough mode only