DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709308
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Simulating the Design 1.6. DisplayPort Intel FPGA IP Design Example Parameters
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Clocking Scheme 2.3. Simulation Testbench
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide

2.3. Simulation Testbench

The simulation testbench simulates the DisplayPort TX serial loopback to RX.
Figure 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram
Table 5.  Testbench Components
Component Description
Video Pattern Generator This generator produces color bar patterns that you can configure. You can parameterize the video format timing.
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX core. The testbench control block also reads the CRC value from both source and sink to make comparisons.
RX Link Speed Clock Frequency Checker This checker verifies if the RX transceiver recovered clock frequency matches the desired data rate.
TX Link Speed Clock Frequency Checker This checker verifies if the TX transceiver recovered clock frequency matches the desired data rate.

The simulation testbench does the following verifications:

Table 6.  Testbench Verifications
Test Criteria Verification
  • Link Training at Data Rate HBR3
  • Read the DPCD registers to check if the DP Status sets and measures both TX and RX Link Speed frequency.
 Integrates Frequency Checker to measure the Link Speed clock's frequency output from the TX and RX transceiver.
  • Run video pattern from TX to RX.
  • Verify the CRC for both source and sink to check if they match
  • Connects video pattern generator to the DisplayPort Source to generate the video pattern.
  • Testbench control next reads out both Source and Sink CRC from DPTX and DPRX registers and compares to ensure both CRC values are identical.
Note: To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
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