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2.3. Simulation Testbench
The simulation testbench simulates the DisplayPort TX serial loopback to RX.
Figure 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram
|Video Pattern Generator||This generator produces color bar patterns that you can configure. You can parameterize the video format timing.|
|Testbench Control||This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX core. The testbench control block also reads the CRC value from both source and sink to make comparisons.|
|RX Link Speed Clock Frequency Checker||This checker verifies if the RX transceiver recovered clock frequency matches the desired data rate.|
|TX Link Speed Clock Frequency Checker||This checker verifies if the TX transceiver recovered clock frequency matches the desired data rate.|
The simulation testbench does the following verifications:
||Integrates Frequency Checker to measure the Link Speed clock's frequency output from the TX and RX transceiver.|
Note: To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
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