DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

Download PDF
ID 709308
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Simulating the Design 1.6. DisplayPort Intel FPGA IP Design Example Parameters
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Clocking Scheme 2.3. Simulation Testbench
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide

1.3. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in Intel® Quartus® Prime software to generate the design example.
Figure 3. Generating the Design Flow
  1. Select Tools > IP Catalog, and select Intel® Agilex™ F-tile as the target device family.
    Note: The design example only supports Intel® Agilex™ F-tile devices.
  2. In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  4. You may select a specific Intel® Agilex™ F-tile device in the Device field, or keep the default Intel® Quartus® Prime software device selection.
  5. Click OK. The parameter editor appears.
  6. Configure the desired parameters for both TX and RX
  7. On the Design Example tab, select DisplayPort SST Parallel Loopback Without PCR.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  9. Click Generate Example Design.
Level Two Title