DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

ID 709308
Date 12/13/2021

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2.2. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel FPGA IP design example.

Figure 7.  Intel® Agilex™ F-tile DisplayPort Transceiver clocking scheme
Table 4.  Clocking Scheme Signals
Clock in diagram Description
SysPLL refclk

F-tile System PLL reference clock which can be any clock frequency that is dividable by System PLL for that output frequency.

In this design example, system_pll_clk_link and rx/tx refclk_link is sharing same SysPLL refclk which is 150Mhz.

It must be a free running clock which is connected from a dedicated transceiver reference clock pin to the input clock port of Reference and System PLL Clocks IP, before connecting the corresponding output port to DisplayPort Phy Top.

The minimum System PLL output frequency to support all DisplayPort rate is 320Mhz.

This design example uses 900 Mhz (highest) output frequency so that SysPLL refclk can be shared with rx/tx refclk_link which is 150 Mhz.

rx_cdr_refclk_link /

Rx CDR and Tx PLL Link refclk which fixed to 150 Mhz to support all DisplayPort data rate.

rx_ls_clkout /


DisplayPort Link Speed Clock to clock DisplayPort IP core. Frequency equivalent to Data Rate divide by parallel data width.


Frequency = data rate / data width

= 8.1G (HBR3) / 40bits

= 202.5 Mhz