DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

ID 709308
Date 12/13/2021

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1.4. Simulating the Design

The DisplayPort Intel® FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.
Figure 4. Design Simulation Flow
  1. Go to Synopsys simulator folder and select VCS.
  2. Run simulation script.
    Source vcs_sim.sh
  3. The script performs Quartus TLG, compiles and run the testbench in the simulator.
  4. Analyze the result.
A successful simulation ends with Source and Sink SRC comparison.