DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

ID 709308
Date 12/13/2021

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2. Parallel Loopback Design Examples

The DisplayPort Intel FPGA IP design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance without a Pixel Clock Recovery (PCR) module at static rate.
Table 3.  DisplayPort Intel FPGA IP Design Example for Intel® Agilex™ F-tile Device
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST parallel loopback without PCR DisplayPort SST HBR3 Simplex Parallel without PCR