DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709308
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Simulating the Design 1.6. DisplayPort Intel FPGA IP Design Example Parameters
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Clocking Scheme 2.3. Simulation Testbench
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide

1.6. DisplayPort Intel FPGA IP Design Example Parameters

Table 2.  DisplayPort Intel FPGA IP Design Example Parameters for Intel® Agilex™ F-tile Device
Parameter Value Description
Available Design Example
Select Design
  • None
  • DisplayPort SST Parallel Loopback without PCR
 Select the design example to be generated.
  • None: No design example is available for the current parameter selection
  • DisplayPort SST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter.
Design Example Files
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.
Synthesis On, Off Turn on this option to generate the necessary files for Intel Quartus Prime compilation and hardware design.
Generated HDL Format
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
Target Development Kit
Select Board
  • No Development Kit
  • Intel Agilex I-Series Development Kit
 Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Intel Agilex I-Series FPGA Development Kit: This option automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit.
    Note: Preliminary Design Example is not functionally verified on hardware in this Quartus release.
  • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.
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