DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

ID 709308
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

1. DisplayPort Intel FPGA IP Design Example Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 21.0.0
The DisplayPort Intel® FPGA IP design examples for Intel® Agilex™ F-tile devices feature a simulating testbench and a hardware design that supports compilation and hardware testing
The DisplayPort Intel® FPGA IP offers the following design examples:
  • DisplayPort SST parallel loopback without a Pixel Clock Recovery (PCR) module at static rate
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Note: Intel® Quartus® Prime 21.4 software version only supports Preliminary Design Example for Simulation, Synthesis, Compilation, and Timing analysis purposes. Hardware functionality is not fully verified.
Figure 1. Development Stages