DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709308
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Simulating the Design 1.6. DisplayPort Intel FPGA IP Design Example Parameters
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Clocking Scheme 2.3. Simulation Testbench
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide

1. DisplayPort Intel FPGA IP Design Example Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 21.0.0
The DisplayPort Intel® FPGA IP design examples for Intel® Agilex™ F-tile devices feature a simulating testbench and a hardware design that supports compilation and hardware testing
The DisplayPort Intel® FPGA IP offers the following design examples:
  • DisplayPort SST parallel loopback without a Pixel Clock Recovery (PCR) module at static rate
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Note: Intel® Quartus® Prime 21.4 software version only supports Preliminary Design Example for Simulation, Synthesis, Compilation, and Timing analysis purposes. Hardware functionality is not fully verified.
Figure 1. Development Stages
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