Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.5. Status and User I/O Elements

The Intel® Stratix® 10 MX FPGA development kit includes status LEDs as listed below.

Table 9.  Board-Specific Status LEDs
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
D14 S10_CONF_DONE AY39 1.8 V
D16 S10_CVP_CONFDONE BC42 1.8 V
D5 OVERTEMPn K11 (MAX10_U27) 1.8 V
D4 PWR_LED_DR B12 (MAX10_U27) 1.8 V
Table 10.  Board-Specific Push Buttons
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
S1 S10_PCIe_PERST_0 AH39 1.8 V
S11 S10_PCIe_PERST_1 BL10 1.8 V
S12 MAX10_Reset N3 (MAX10_U24) 1.8 V
S10 CPU_Reset BL14 1.8 V

User-Defined LEDs

The Intel® Stratix® 10 MX FPGA development kit includes a set of four user-defined LEDs. The LEDs illuminate (turn ON) when a logic 0 is driven, and turn OFF when a logic 1 is driven. There are no board-specific functions for these LEDs.

Table 11.  User-Defined LEDs
Board Reference Schematic Signal Names FPGA Pin Number I/O Standard
D7 S10_LED0 BG12 1.8 V
D8 S10_LED1 BF12 1.8 V
D9 S10_LED2 BG11 1.8 V
D10 S10_LED3 BH11 1.8 V
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