Intel® Stratix® 10 MX FPGA Development Kit User Guide

Download PDF
ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.3. Intel® MAX® 10 FPGA Power Manager

This development kit utilizes the Intel® MAX® 10 FPGA 10M16SAU169 FPGA as Power Manager (U27) for the following purposes:
  • Power Sequencing Control
  • Power Discharging Control
  • Voltage Monitoring
  • Fan Control
Table 7.   Intel® MAX® 10 FPGA Power Manager Pin Table
Schematic Signal Name Pin Number I/O Standard Description
3p3V_EN L5 3.3V Enable or disable 3.3V power rail
S10_VCC_EN M4 3.3V Enable or disable FPGA Core power rail
S10_VCCERAM_EN L4 3.3V Enable or disable VCCERAM power rail
S10_VCCRL_EN M5 3.3V Enable or disable Left side Receiver Power VCCRL power rail
S10_VCCRR K5 3.3V Enable or disable Right side Receiver Power VCCRR power rail
S10_VCCT N4 3.3V Enable or disable Transmitter Power VCCT power rail
1p8V_EN J5 3.3V Enable or disable 1.8V power rail
VCCIO_UIB_EN N5 3.3V Enable or disable VCCIO_UIB power rail
VCCM_EN N6 3.3V Enable or disable VCCM power rail
1p2V_DDR4_EN N7 3.3V Enable or disable 1.2V for DDR4 power rail
HILO_VDDQ_EN M7 3.3V Enable or disable VDDQ power rail for HILO memory
HILO_VDD_EN N8 3.3V Enable or disable VDD power rail for HILO memory
2p5V_EN J6 3.3V Enable or disable 2.5V power rail
ZQSFP0_PWR_EN M8 3.3V Enable or disable the power to QSFP_0 module
ZQSFP1_PWR_EN K6 3.3V Enable or disable the power to QSFP_1 module
DIMM_VTT_EN M9 3.3V Enable or disable the termination power for DDR4 DIMM
COMP_VTT_EN J7 3.3V Enable or disable the termination power for on-board DDR4 memory
POWER_ON M13 3.3V Signal from power input circuit to Intel® MAX® 10 for starting power sequencing
1p2V_DDR4_DIS N2 3.3V Signal to enable discharge circuit for 1.2 V DDR4 power rail
VCCIO_UIB_DIS N3 3.3V Signal to enable discharge circuit for 1.2 V VCCIO UIB power rail
HILO_VDD_DIS M11 3.3V Signal to enable discharge circuit for HILO VDD power rail
HILO_VDDQ_DIS L11 3.3V Signal to enable discharge circuit for HILO VDDQ power rail
VCCM_DIS K8 3.3V Signal to enable discharge circuit for HBM's VCCM power rail
1p8V_DIS G9 3.3V Signal to enable discharge circuit for 1.8 V power rail
VCCRL_GXB_DIS G10 3.3V Signal to enable discharge circuit for VCCRL_GXB power rail
VCCRR_GXB_DIS F13 3.3V Signal to enable discharge circuit for VCCRR_GXB power rail
VCCT_DIS E13 3.3V Signal to enable discharge circuit for VCCT_GXB power rail
VCCERAM_DIS F9 3.3V Signal to enable discharge circuit for VCCERAM power rail
2p5V_DIS F10 3.3V Signal to enable discharge circuit for 2.5V power rail
3p3V_DIS C10 3.3V Signal to enable discharge circuit for 3.3V power rail
I2C_3V3_SDA M12 3.3V I2C signals
I2C_3V3_SCL N9 3.3V I2C signals
PWR_MAX10_JTAG_TMS G1 3.3V JTAG signals
PWR_MAX10_JTAG_TCK G2 3.3V JTAG signals
PWR_MAX10_JTAG_TDI F5 3.3V JTAG signals
PWR_MAX10_JTAG_TDO F6 3.3V JTAG signals
3p3V _PG A6 3.3V Power Good signal from 3.3V power supply
S10_VCC_PG A9 3.3V Power Good signal from VCC Core power supply
S10_VCCERAM_PG B10 3.3V Power Good signal from VCCERAM power supply
S10_VCCRL_PG A10 3.3V Power Good signal from VCCRL power supply
S10_VCCRR_PG A11 3.3V Power Good signal from VCCRR power supply
S10_VCCT_PG E8 3.3V Power Good signal from VCCT power supply
1p8V_PG A4 3.3V Power Good signal from 1.8V power supply
1p2V_VCCIO_UIB_PG A7 3.3V Power Good signal from VCCIO_UIB power supply
VCCM_PG A4 3.3V Power Good signal from VCCM power supply
HILO_VDD_PG B5 3.3V Power Good signal from VDD power supply for HILO
HILO_VDDQ_PG A3 3.3V Power Good signal from VDDQ power supply for HILO
1p2V_DDR4_PG E6 3.3V Power Good signal from 1.2V power supply for DDR4 Memory
12V_G1_PG F12 3.3V Power Good signal from 12V Group1 of input power circuit
12V_G2_PG E12 3.3V Power Good signal from 12V Group2 of input power circuit
5V_PG C13 3.3V Power Good signal from 5V power supply
2p5V_PG E10 3.3V Power Good signal from 2.5V power supply
COMP_VTT_PG F8 3.3V Power Good signal from on-board DDR4 termination power supply
DIMM_VTT_PG B13 3.3V Power Good signal from DIMM DDR4 termination power supply
12V_G1_UV_PG D9 3.3V Power Good signal from 12V Group 1's Under-Voltage monitor
12V_G1_OV_PG D12 3.3V Power Good signal from 12V Group 1's Over-Voltage monitor
S10_VCCFAULT B4 3.3V Fault signal from FPGA VCC Core power supply
EM_PMBUS_ALERTn B11 3.3V Alert signal from Enpirion power regulators
LT_PMBUS_ALERTn C12 3.3V Alert signal from Linear Technology power regulators
ZQSFP0_FAULT_N C11 3.3V Fault signal from QSFP_0 module
ZQSFP1_FAULT_N A12 3.3V Fault signal from QSFP_1 module
PCIE_RT_PRSNT2n D11 3.3V PCIE Root Port Present signal
PCIE_EP_PERSTN H4 3.3V PCIE End Point Present signal
PWR_LED_DR B12 3.3V Power LED drive signal
PWR_GOOD E9 3.3V Power Good signal of all power supplies to Intel® MAX® 10 System Controller
OVERTEMPn K11 3.3V Over Temperature signal from Board Temp sensor chip U29
TSENSE_ALERTn L12 3.3V Temperature Sense Alert signal from Board Temp sensor chip U29
FAN_CTRL K12 3.3V Fan speed control signal to cooling fans driver
S10MX_VCC D2 Analog FPGA Core Voltage sensing input
S10_VCCERAM D1 Analog VCCERAM Voltage sensing input
S10_VCCRL_GXB C2 Analog FPGA Left side receiver voltage sensing input
S10_VCCRR_GXB E3 Analog FPGA Right side receiver voltage sensing input
S10_VCCT_GXB E4 Analog FPGA Transmitter voltage sensing input
1p2V_VCCIO_UIB C1 Analog 1.2V VCCIO UIB Voltage sensing input
1p8V B1 Analog 1.8V Voltage sensing input
1p2V_DDR4 F1 Analog 1,2V for DDR4 voltage sensing input
VCCM E1 Analog VCCM for HMB voltage sensing input
Level Two Title