Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 11/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 MX FPGA Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. MAX® 10 FPGA System Controller 4.3. MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C 4.6.6. Flash Memory Flash Flash Programming
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board 5.2. Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 MX FPGA Development Kit User Guide

4.6.6. Flash Memory

Flash

The Stratix® 10 MX FPGA development kit supports one 2 Gb CFI-compatible NOR-type device (P/N: MT25Qu02GCBB3E12) for non-volatile storage of FPGA configuration data, board information, test application data and user code space. This device is controlled by the FPGA’s SDM.

Table 25.  Flash Memory (U14) Pin Connections
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard Description
D3 AS_DATA0 BH41 1.8V Data
D2 AS_DATA1 BG42 1.8V Data
C4 AS_DATA2 BF42 1.8V Data
D4 AS_DATA3 BC40 1.8V Data
B2 AS_CLK AT37 1.8V Clock from FPGA
C2 AS_CS0_MSEL0 AR37 1.8V Chip Select signal

Flash Programming

You can use the Quartus® Prime Programmer to program the flash with your Programmer Object File (.pof).

Ensure the following conditions are met before you proceed

  1. The Quartus® Prime Programmer and the Intel® FPGA Download Cable II driver are installed on the host computer.
  2. If you are using an external JTAG programmer, ensure the Intel® FPGA Download Cable II is connected to the board through the 10-pin female connector. Verify that the Intel® FPGA Download Cable II LED for proper connection to the host computer through a micro-USB cable.
  3. Power to the board is on, and no other applications that use the JTAG chain are running.
  4. The design running in the FPGA does not drive the FM bus.

Execute the steps below to program the Flash Memory

  1. Start the Quartus® Prime Programmer.
  2. Click Auto Detect to display the devices in the JTAG chain.
  3. Select the flash attached to the Stratix® 10 MX FPGA and then click Change File and select the path to the desired .pof. If the flash is not detected, configure the FPGA with any configuration image which does not drive the flash signals and then go to step 2.
  4. Turn on the Program/Configure option for the added file.
  5. Click Start to program the selected file to flash. Programming is complete when the progress bar reaches 100%. If flash programming fails, change the TCK frequency to a lower frequency (16 MHz or 6 MHz). Run the command below in the Nios® II command shell. jtag --setparam <cable> JtagClock <frequency><Units>. For example: jtagconfig --setparam 1 JtagClock 16M and then go to Step 4.
    Attention: Using the Quartus® Prime Programmer to program a device on the board causes other JTAG- based applications such as the Board Test System and the Power Monitor to lose their connection to the board. Restart those applications after programming is complete.
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