Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.1. Components Overview

Table 5.  Development Kit Components Table
Board Reference Type Description
Featured Devices
U1 FPGA

Intel® Stratix® 10 MX FPGA1

  • Adaptive Logic Modules (ALM): 702,720
  • Logic Elements (LE): 2,073K
  • Registers: 2,810,880
  • M20K Memory Blocks: 6,847
  • Transceiver Count: 96
  • Package Type: 2597 BGA
  • HMB2 DRAM (GB): 8 or 16
U11 FPGA

Intel® MAX® 10 FPGA, 4K LEs, 169 FBGA (System)

U27 FPGA Intel® MAX® 10, 16K LEs, 169 FBGA (Power)
Configuration and Setup Elements
J15 On-board Intel® FPGA Download Cable II

Micro-USB 2.0 connector for programming and debugging the FPGA.

SW2 JTAG Bypass DIP Switch

Enable and disable devices in the JTAG chain. This switch is located on the back of the board.

SW1 I2C Bus Selection Switch Enable or Disable the I2C Bus for Clock chip, 3.3 V VRM, Main I2C, and Intel® Stratix® 10 FPGA
S10 CPU reset push button The default reset for the FPGA logic.
S1 PCIe PERST 0 push button

This push button connects to Intel® Stratix® 10 FPGA's NPERSTL0 pin.

S11 PCIe PERST 1 push button

This push button connects to Intel® Stratix® 10 FPGA's NPERSTR1 pin.

S12 Intel® MAX® 10 Reset Push Button The default reset for the Intel® MAX® 10 FPGA System Controller
Status Elements
D14 Configuration Done LED Illuminates when FPGA configuration is completed
D16 CvP Done LED Illuminates when CvP process is completed
D4 Power LED (Blue) Illuminates when board is powered on.
D5 Temperature LED (Green)

Illuminates when an over temperature condition occurs for the FPGA device. Ensure that an adequate heatsink/fan is properly installed.

D7, D8, D9, D10 User-defined LEDs Four green color user LEDs. Illuminate when driven low.
Clock Circuits
U17 Intel® MAX® 10 Reference Clock

Si510 Crystal Oscillator provides reference clocks for Intel® MAX® 10 devices

Default Frequencies are:
  • Out0= 50.00 MHz
  • Out1= 50.00 MHz
U16 Programmable Clock Generator

Si5341A Programmable Clock Generator by the clock control GUI

Default Frequencies are:
  • Out0= 644.53125 MHz
  • Out1= 644.53125 MHz
  • Out2= 100 MHz
  • Out3= 100 MHz
  • Out4= 100 MHz
  • Out5= 100 MHz
  • Out6= 100 MHz
  • Out7= 100 MHz
  • Out8= 100 MHz
  • Out9= 100 MHz
U18 Programmable Clock Generator

Si5338A Programmable Clock Generator by the Clock Control GUI

Default Frequencies are:
  • CLK0= 50 MHz
  • CLK1= 100 MHz
  • CLK2= 125 MHz
  • CLK3= 100 MHz
U19 Programmable Clock Generator

Si5338B Programmable Clock Generator by the Clock Control GUI

Default Frequencies are:
  • CLK0= 133.333 MHz
  • CLK1= 133.333 MHz
  • CLK2= 133.333 MHz
  • CLK3= Not Used
Transceiver Interfaces
J6 PCIe* x16 gold fingers PCIe* TX/RX x16 interface from FPGA bank 1C, 1D, 1E
J7 PCIe* x16 Root Port Connector PCIe* TX/RX x16 interface from FPGA bank 4C, 4D, 4E
J4 QSFP Connector Four TX/RX channels from FPGA Bank 1F
J5 QSFP Connector Four TX/RX channels from 4F from FPGA bank 4F
General User Input/Output
D7, D8, D9. D10 User defined LEDs Four green color user LEDs. Illuminates when driven low.
Memory Devices
J2 HiLo Connector

One x72 memory interface supporting DDR3 (x72), DDR4 (x72), QDR-IV (x36) and RLDRAM3 (x36).

This development kit includes one plugin modules (daughtercards) that use the HiLo connector: DDR4 memory (x72) 1333 MHz

J1 DDR4, DDR-T, DIMM Socket
One X72 memory interface supporting DDR4 (x72) or DDR-T memory module.
  • DDR4 memory (x72) 1333 MHz
  • DDR-T memory (requires DDR-T IP)
U3, U4, U5, U6, U7 On-board DDR4 memory On-board DDR4 memory (x72) 1333 MHz
Communication Ports
J6 PCI Express* x16 Edge Connector

Gold-plated edge fingers for up to x16 signaling in either Gen1, Gen2 or Gen3 mode.

J7 PCI Express* x16 Root Port Connector Standard PCI Express* Gen3 x16 Connector for connecting PCIe* Endpoint card.
J4 QSFP interface Provides four transceiver channels per port for a 100G QSFP module
J5 QSFP interface Provides four transceiver channels per port for a 100G QSFP module
J13 Linear Tech VRM PMBus Port Provides PMBus connection using dongle from Linear Tech.
J12 Enpirion VRM PMBus Port Provides PMBus connection using dongle from Intel® Enpirion®
J9 External JTAG Port This port allows the use of Intel® FPGA Download Cable II dongle to access the JTAG links on the board. Connection to this port automatically disable the internal Intel® FPGA Download Cable II JTAG.
J15 Micro-USB Connector

Embedded Intel® FPGA Download Cable II JTAG for programming the FPGA via a USB cable.

Power Supply
J6 PCI Express* edge connector Interfaces to a PCI Express root port such as an appropriate PC motherboard.
J11 DC Input Jack

Accepts a 12 V DC power supply when powering the board from the provided power brick for lab bench operation. When operating from the PCIe* slot, this input must also be connected to the 8-pin Aux PCIe* power connector provided by the PC system along with J11, or else the board does not power on.

SW3 Power Switch Switch to power ON or OFF the board when supplied from the DC input jack.
Related Information
1 Refer to Overview for the part number for your specific board
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