Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

1.1. General Development Kit Description

Figure 1.  Intel® Stratix® 10 MX FPGA Development Kit Block Diagram

Feature Summary

  • Intel® Stratix® 10 MX FPGA device
    • 0.85 V - 0.89 V VID-adjustable VCC core, 1 mm pitch, 2597 pin BGA
    • H-Tile transceivers capable of 28.3 gigabit per second (Gbps) data rates
    • HBM2 embedded memory tiles: 8 GB (4 GB x 2) or 16 GB (8 GB x 2)
  • FPGA Configuration
    • Partial reconfiguration support
    • 2 gigabits (Gb) QSPI Flash
    • Storage for two configuration images in flash (Factory and User)
    • JTAG header for device programming
    • Built-in Intel® FPGA Download Cable II for device programming
  • Programmable Clock Sources
    • 644.53125 MHz Differential LVDS for QSFP
    • 100.000 MHz Differential LVDS for PCIe*
    • 133.333 MHz Differential LVDS to Memory
    • 125 MHz Configuration Clock
  • Transceiver Interfaces
    • PCIe* x16 interface supporting Gen3 End-Point mode connected to a x16 PCIe* edge connector (gold edge fingers)
    • PCIe* x16 interface supporting Gen3 Root-Port mode connected to a x16 straddle-mount PCIe* edge connector
    • 2x standard QSFP28 optical module interfaces connected to the FPGA H-Tile transceivers
  • Memory Interfaces
    • One on-board independent single rank DDR4 x72 (ECC) channels operating at 1333 MHz (DDR4-2666)
    • One DIMM socket supporting DDR4 DIMM or DDR-T DIMM
    • One HiLo connector supporting DDR4 and QDR-IV
  • Communication Ports
    • 2x QSFP28 optical interface port
    • JTAG header
    • USB (Micro) on-board Intel® FPGA Download Cable II
  • Buttons, Switches and LEDs
    • System Reset Pushbutton
    • CPU Reset Pushbutton
    • PCIe* Reset Pushbutton
    • Four dedicated User LEDs
    • Two dedicated configuration status LEDs
  • Heatsink and Fan
    • Air-cooled heatsink assembly
    • Red Over-Temperature Warning LED Indicator
  • Power
    • PCIe* input power including required 2 x 4 Aux power connector
    • Blue Power-On LED
    • On/Off Slide Power Switch for bench-top operation
    • On board Power Measurement Circuitry
  • Mechanical
    • PCIe* standard height form factor
    • 4.376” x 10.8” board size
    • 3 Slots height requirement (with Air-cooled thermal solution)
  • Operating Environment
    • Maximum ambient temperature of 0 °C - 35 °C
Level Two Title