Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.6.1. PCI Express

The Intel® Stratix® 10 MX FPGA development kit supports two PCI Express* interfaces: PCI Express* End Point via a standard PCI Express* x16 Edge connector and PCI Express* Root Port via a standard PCI Express* x16 connector.

The Intel® Stratix® 10 MX FPGA development board is designed to fit entirely into a PC motherboard with a x16 PCI Express* slot that can accommodate a full height, 3-slot long form factor add-in card. This interface uses the PCI Express hard IP block on the Intel® Stratix® 10 MX FPGA, saving logic resources for the user logic application. The PCI Express* edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.

The PCI Express* interface supports bus width of x16 by using the PCIe* Intel® FPGA IP. The PCI Express* edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 40 Gbps full-duplex (Gen1), 5.0 Gbps/lane for maximum of 80 Gbps full- duplex (Gen 2), or 8.0 Gbps/lane for a maximum of 128 Gbps full-duplex (Gen3).

The power for the board can be sourced entirely from the PC host when installed into a PC motherboard with the PC's 2x4 ATX auxiliary power connected to the 12V ATX inputs (J11) of the Intel® Stratix® 10 MX development kit.

The REFCLK_PCIE_EP_EDGE_P/N signal is a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector. This signal connects directly to an Intel® Stratix® 10 MX FPGA REFCLK input pin pair using DC coupling.

This clock is terminated on the motherboard, and therefore no on-board termination is required. This clock can have spread-spectrum properties that change its period between 9.847 ps and 10.203 ps.

The I/O standard is High-Speed Current Steering Logic (HCSL). The JTAG and SMB are optional signals in the PCI Express* TDI to PCI Express* TDO and are not used on this board. The SMB signals are wired to the Intel® Stratix® 10 MX FPGA but are not required for normal operation.

Table 12.   PCI Express* (J6) End Point Interface Pin Connections
Receive Bus Schematic Signal Name FPGA Pin Number I/O Standard Description
A11 PCIE_EP_PERST_N - - Connect to PRSNT2n_x16 (pin B81)
B17 PCIE_PRSNT2n_X1 - - No connect
B31 PCIE_PRSNT2n_X4 - - No connect
B48 PCIE_PRSNT2n_X8 - - No connect
B81 PCIE_PRSNT2n_X16 - - Connect to PCIE_PRSNT1n ( pin A11)
B15 PCIE_EP_TX_N0 BH44 1.4 V PCML Transmit bus
B20 PCIE_EP_TX_N1 BJ46 1.4 V PCML Transmit bus
B24 PCIE_EP_TX_N2 BG46 1.4 V PCML Transmit bus
B28 PCIE_EP_TX_N3 BF44 1.4 V PCML Transmit bus
B34 PCIE_EP_TX_N4 BE46 1.4 V PCML Transmit bus
B38 PCIE_EP_TX_N5 BD44 1.4 V PCML Transmit bus
B42 PCIE_EP_TX_N6 BB44 1.4 V PCML Transmit bus
B46 PCIE_EP_TX_N7 BC46 1.4 V PCML Transmit bus
B51 PCIE_EP_TX_N8 BA46 1.4 V PCML Transmit bus
B55 PCIE_EP_TX_N9 AY44 1.4 V PCML Transmit bus
B59 PCIE_EP_TX_N10 AW46 1.4 V PCML Transmit bus
B63 PCIE_EP_TX_N11 AV44 1.4 V PCML Transmit bus
B67 PCIE_EP_TX_N12 AU46 1.4 V PCML Transmit bus
B71 PCIE_EP_TX_N13 AT44 1.4 V PCML Transmit bus
B75 PCIE_EP_TX_N14 AR46 1.4 V PCML Transmit bus
B79 PCIE_EP_TX_N15 AP44 1.4 V PCML Transmit bus
B14 PCIE_EP_TX_P0 BH45 1.4 V PCML Transmit bus
B19 PCIE_EP_TX_P1 BJ47 1.4 V PCML Transmit bus
B23 PCIE_EP_TX_P2 BG47 1.4 V PCML Transmit bus
B27 PCIE_EP_TX_P3 BF45 1.4 V PCML Transmit bus
B33 PCIE_EP_TX_P4 BE47 1.4 V PCML Transmit bus
B37 PCIE_EP_TX_P5 BD45 1.4 V PCML Transmit bus
B41 PCIE_EP_TX_P6 BB45 1.4 V PCML Transmit bus
B45 PCIE_EP_TX_P7 BC47 1.4 V PCML Transmit bus
B50 PCIE_EP_TX_P8 BA47 1.4 V PCML Transmit bus
B54 PCIE_EP_TX_P9 AY45 1.4 V PCML Transmit bus
B58 PCIE_EP_TX_P10 AW47 1.4 V PCML Transmit bus
B62 PCIE_EP_TX_P11 AV45 1.4 V PCML Transmit bus
B66 PCIE_EP_TX_P12 AU47 1.4 V PCML Transmit bus
B70 PCIE_EP_TX_P13 AT45 1.4 V PCML Transmit bus
B74 PCIE_EP_TX_P14 AR47 1.4 V PCML Transmit bus
B78 PCIE_EP_TX_P15 AP45 1.4 V PCML Transmit bus
A17 PCIE_EP_RX_N0 BL46 1.4 V PCML Receive bus
A22 PCIE_EP_RX_N1 BK48 1.4 V PCML Receive bus
A26 PCIE_EP_RX_N2 BH48 1.4 V PCML Receive bus
A30 PCIE_EP_RX_N3 BG50 1.4 V PCML Receive bus
A36 PCIE_EP_RX_N4 BF48 1.4 V PCML Receive bus
A40 PCIE_EP_RX_N5 BE50 1.4 V PCML Receive bus
A44 PCIE_EP_RX_N6 BD48 1.4 V PCML Receive bus
A48 PCIE_EP_RX_N7 BC50 1.4 V PCML Receive bus
A53 PCIE_EP_RX_N8 BB48 1.4 V PCML Receive bus
A57 PCIE_EP_RX_N9 BA50 1.4 V PCML Receive bus
A61 PCIE_EP_RX_N10 AY48 1.4 V PCML Receive bus
A65 PCIE_EP_RX_N11 AW50 1.4 V PCML Receive bus
A69 PCIE_EP_RX_N12 AV48 1.4 V PCML Receive bus
A73 PCIE_EP_RX_N13 AU50 1.4 V PCML Receive bus
A77 PCIE_EP_RX_N14 AT48 1.4 V PCML Receive bus
A81 PCIE_EP_RX_N15 AR50 1.4 V PCML Receive bus
A16 PCIE_EP_RX_P0 BL47 1.4 V PCML Receive bus
A21 PCIE_EP_RX_P1 BK49 1.4 V PCML Receive bus
A25 PCIE_EP_RX_P2 BH49 1.4 V PCML Receive bus
A29 PCIE_EP_RX_P3 BG51 1.4 V PCML Receive bus
A35 PCIE_EP_RX_P4 BF49 1.4 V PCML Receive bus
A39 PCIE_EP_RX_P5 BE51 1.4 V PCML Receive bus
A43 PCIE_EP_RX_P6 BD49 1.4 V PCML Receive bus
A47 PCIE_EP_RX_P7 BC51 1.4 V PCML Receive bus
A52 PCIE_EP_RX_P8 BB49 1.4 V PCML Receive bus
A56 PCIE_EP_RX_P9 BA51 1.4 V PCML Receive bus
A60 PCIE_EP_RX_P10 AY49 1.4 V PCML Receive bus
A64 PCIE_EP_RX_P11 AW51 1.4 V PCML Receive bus
A68 PCIE_EP_RX_P12 AV49 1.4 V PCML Receive bus
A72 PCIE_EP_RX_P13 AU51 1.4 V PCML Receive bus
A76 PCIE_EP_RX_P14 AT49 1.4 V PCML Receive bus
A80 PCIE_EP_RX_P15 AR51 1.4 V PCML Receive bus
B11 PCIE_EP_WAKEN BH16 1.8V Wake signal
Table 13.   PCI Express* Root Port Interface (J7) Pin Connections
Receive Bus Schematic Signal Name FPGA Pin Number I/O Standard Description
A1 PCIE_PRSNT1n - - Connect to PCIE_PRSNT2n_X16
B17 PCIE_PRSNT2n_X1 - - No connect
B31 PCIE_PRSNT2n_X4 - - No connect
B48 PCIE_PRSNT2n_X8 - - No connect
B81 PCIE_PRSNT2n_X16 - - Connect to PCIE_PRSNT1n
B15 PCIE_RT_TX_N0 BL6 1.4 V PCML Transmit bus
B20 PCIE_RT_TX_N1 BK4 1.4 V PCML Transmit bus
B24 PCIE_RT_TX_N2 BH4 1.4 V PCML Transmit bus
B28 PCIE_RT_TX_N3 BG2 1.4 V PCML Transmit bus
B34 PCIE_RT_TX_N4 BF4 1.4 V PCML Transmit bus
B38 PCIE_RT_TX_N5 BE2 1.4 V PCML Transmit bus
B42 PCIE_RT_TX_N6 BD4 1.4 V PCML Transmit bus
B46 PCIE_RT_TX_N7 BC2 1.4 V PCML Transmit bus
B51 PCIE_RT_TX_N8 BB4 1.4 V PCML Transmit bus
B55 PCIE_RT_TX_N9 BA2 1.4 V PCML Transmit bus
B59 PCIE_RT_TX_N10 AY4 1.4 V PCML Transmit bus
B63 PCIE_RT_TX_N11 AW2 1.4 V PCML Transmit bus
B67 PCIE_RT_TX_N12 AV4 1.4 V PCML Transmit bus
B71 PCIE_RT_TX_N13 AU2 1.4 V PCML Transmit bus
B75 PCIE_RT_TX_N14 AT4 1.4 V PCML Transmit bus
B79 PCIE_RT_TX_N15 AR2 1.4 V PCML Transmit bus
B14 PCIE_RT_TX_P0 BL5 1.4 V PCML Transmit bus
B19 PCIE_RT_TX_P1 BK3 1.4 V PCML Transmit bus
B23 PCIE_RT_TX_P2 BH3 1.4 V PCML Transmit bus
B27 PCIE_RT_TX_P3 BG1 1.4 V PCML Transmit bus
B33 PCIE_RT_TX_P4 BF3 1.4 V PCML Transmit bus
B37 PCIE_RT_TX_P5 BE1 1.4 V PCML Transmit bus
B41 PCIE_RT_TX_P6 BB8 1.4 V PCML Transmit bus
B45 PCIE_RT_TX_P7 BC5 1.4 V PCML Transmit bus
B50 PCIE_RT_TX_P8 BA5 1.4 V PCML Transmit bus
B54 PCIE_RT_TX_P9 AY7 1.4 V PCML Transmit bus
B58 PCIE_RT_TX_P10 AW5 1.4 V PCML Transmit bus
B62 PCIE_RT_TX_P11 AV7 1.4 V PCML Transmit bus
B66 PCIE_RT_TX_P12 AV3 1.4 V PCML Transmit bus
B70 PCIE_RT_TX_P13 AU1 1.4 V PCML Transmit bus
B74 PCIE_RT_TX_P14 At3 1.4 V PCML Transmit bus
B78 PCIE_RT_TX_P15 AR1 1.4 V PCML Transmit bus
A17 PCIE_RT_RX_N0 BH7 1.4 V PCML Receive bus
A22 PCIE_RT_RX_N1 BJ5 1.4 V PCML Receive bus
A26 PCIE_RT_RX_N2 BG5 1.4 V PCML Receive bus
A30 PCIE_RT_RX_N3 BF7 1.4 V PCML Receive bus
A36 PCIE_RT_RX_N4 BE5 1.4 V PCML Receive bus
A40 PCIE_RT_RX_N5 BD7 1.4 V PCML Receive bus
A44 PCIE_RT_RX_N6 BB7 1.4 V PCML Receive bus
A48 PCIE_RT_RX_N7 BC6 1.4 V PCML Receive bus
A53 PCIE_RT_RX_N8 BA6 1.4 V PCML Receive bus
A57 PCIE_RT_RX_N9 AY8 1.4 V PCML Receive bus
A61 PCIE_RT_RX_N10 AW6 1.4 V PCML Receive bus
A65 PCIE_RT_RX_N11 AV8 1.4 V PCML Receive bus
A69 PCIE_RT_RX_N12 AU6 1.4 V PCML Receive bus
A73 PCIE_RT_RX_N13 AT8 1.4 V PCML Receive bus
A77 PCIE_RT_RX_N14 AR6 1.4 V PCML Receive bus
A81 PCIE_RT_RX_N15 AP8 1.4 V PCML Receive bus
A16 PCIE_RT_RX_P0 BH8 1.4 V PCML Receive bus
A21 PCIE_RT_RX_P1 BJ5 1.4 V PCML Receive bus
A25 PCIE_RT_RX_P2 BG6 1.4 V PCML Receive bus
A29 PCIE_RT_RX_P3 BF8 1.4 V PCML Receive bus
A35 PCIE_RT_RX_P4 BE6 1.4 V PCML Receive bus
A39 PCIE_RT_RX_P5 BD8 1.4 V PCML Receive bus
A43 PCIE_RT_RX_P6 BB8 1.4 V PCML Receive bus
A47 PCIE_RT_RX_P7 BC5 1.4 V PCML Receive bus
A52 PCIE_RT_RX_P8 AY7 1.4 V PCML Receive bus
A56 PCIE_RT_RX_P9 AW5 1.4 V PCML Receive bus
A60 PCIE_RT_RX_P10 AW5 1.4 V PCML Receive bus
A64 PCIE_RT_RX_P11 AV7 1.4 V PCML Receive bus
A68 PCIE_RT_RX_P12 AU5 1.4 V PCML Receive bus
A72 PCIE_RT_RX_P13 AT7 1.4 V PCML Receive bus
A76 PCIE_RT_RX_P14 AR5 1.4 V PCML Receive bus
A80 PCIE_RT_RX_P15 AP7 1.4 V PCML Receive bus
B11 PCIE_RT_WAKEN B4 1.8V Wake signal
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