Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.2. Intel® MAX® 10 FPGA System Controller

This development kit utilizes the Intel® MAX® 10 FPGA (10M04SCU169) as system controller for the following purposes:
  • On-board Intel® FPGA Download Cable
  • JTAG Switch
  • I2C Bus Control
  • Control registers for all programmable clocks
  • Control registers for QSFP and PCIe* interfaces
Table 6.   Intel® MAX® 10 FPGA System Controller Device Pin Table
Schematic Signal Name Pin Number I/O Standard Description
FX2_PA0 K6 3.3V Intel® MAX® 10 to USB PHY Download Cable bus A
FX2_PA1 M4 3.3V Intel® MAX® 10 to USB PHY Download Cable bus A
FX2_PA2 M5 3.3V Intel® MAX® 10 to USB PHY Download Cable bus A
FX2_PA3 K5 3.3V Intel® MAX® 10 to USB PHY Download Cable bus A
FX2_PA4 L4 3.3V Intel® MAX® 10 to USB PHY Download Cable bus A
FX2_PA5 J5 3.3V Intel® MAX® 10 to USB PHY Download Cable bus A
FX2_PA6 N4 3.3V Intel® MAX® 10 to USB PHY Download Cable bus A
FX2_PA7 J7 3.3V Intel® MAX® 10 to USB PHY Download Cable bus A
FX2_PB0 K7 3.3V Intel® MAX® 10 to USB PHY Download Cable bus B
FX2_PB1 N9 3.3V Intel® MAX® 10 to USB PHY Download Cable bus B
FX2_PB2 N7 3.3V Intel® MAX® 10 to USB PHY Download Cable bus B
FX2_PB3 N6 3.3V Intel® MAX® 10 to USB PHY Download Cable bus B
FX2_PB4 M13 3.3V Intel® MAX® 10 to USB PHY Download Cable bus B
FX2_PB5 N5 3.3V Intel® MAX® 10 to USB PHY Download Cable bus B
FX2_PB6 M9 3.3V Intel® MAX® 10 to USB PHY Download Cable bus B
FX2_PB7 M11 3.3V Intel® MAX® 10 to USB PHY Download Cable bus B
USB_MAX_TCK G2 3.3V Intel® MAX® 10 JTAG to USB PHY FX2_PD0
USB_MAX_TMS G1 3.3V Intel® MAX® 10 JTAG to USB PHY FX2_PD1
USB_MAX_TDI F5 3.3V Intel® MAX® 10 JTAG to USB PHY FX2_PD2
USB_MAX_TDO F6 3.3V Intel® MAX® 10 JTAG to USB PHY FX2_PD3
FX2_PD4 N8 3.3V Intel® MAX® 10 to USB PHY Download Cable bus D
FX2_PD5 M7 3.3V Intel® MAX® 10 to USB PHY Download Cable bus D
FX2_PD6 M8 3.3V Intel® MAX® 10 to USB PHY Download Cable bus D
FX2_PD7 J6 3.3V Intel® MAX® 10 to USB PHY Download Cable bus D
FX2_RESETn N3 3.3V USB PHY Reset
FX2_FLAGA J8 3.3V USB PHY FIFO output Flag signal to Intel® MAX® 10
FX2_FLAGB L5 3.3V USB PHY FIFO output Flag signal to Intel® MAX® 10
FX2_FLAGC L11 3.3V USB PHY FIFO output Flag signal to Intel® MAX® 10
FX2_SLRDn M12 3.3V USB PHY Read signal
FX2_SLWRn N10 3.3V USB PHY Write signal
FX2_SCL K8 3.3V USB PHY I2C signal
FX2_SDA L10 3.3V USB PHY I2C signal
USB_T_CLK H6 3.3V Interface Clock from USB PHY
USB_DISABLEn N2 3.3V External JTAG signal to Intel® MAX® 10 for disabling internal USB Blaster circuit
EM_PMBUS_ALERTn L1 3.3V PMBus Alert signal from Intel® Enpirion® Power Regulator
LT_PMBUS_ALERTn N11 3.3V PMBus Alert signal from LT Power regulator
ZQSFP0_1V8_RESET_L K10 1.8V QSFP module 0 Reset signal ( Intel® MAX® 10 to FPGA)
ZQSFP0_1V8_MODPRS_L K11 1.8V QSFP module 0 control signal ( Intel® MAX® 10 to FPGA)
ZQSFP0_1V8_LPMODE J10 1.8V QSFP module 0 Low Power signal ( Intel® MAX® 10 to FPGA)
ZQSFP0_1V8_INT_L L12 1.8V QSFP module 0 interrupt signal ( Intel® MAX® 10 to FPGA)
ZQSFP0_1V8_MODSEL_L H9 1.8V QSFP module 0 Mode Select signal ( Intel® MAX® 10 to FPGA)
ZQSFP1_1V8_RESET_L K12 1.8V QSFP module 1 Reset signal ( Intel® MAX® 10 to FPGA)
ZQSFP1_1V8_MODPRS_L L13 1.8V QSFP module 1 Present signal ( Intel® MAX® 10 to FPGA)
ZQSFP1_1V8_LPMODE J12 1.8V QSFP module 1 Low Power signal ( Intel® MAX® 10 to FPGA)
ZQSFP1_1V8_INT_L J9 1.8V QSFP module 1 interrupt signal ( Intel® MAX® 10 to FPGA)
ZQSFP1_1V8_MODSEL_L G13 1.8V QSFP module 1 Mode Select signal ( Intel® MAX® 10 to FPGA)
ZQSFP0_3V3_RESET_L B10 3.3V QSFP module 0 Reset signal to Intel® MAX® 10
ZQSFP0_3V3_MODPRS_L A10 3.3V QSFP module 0 control signal to Intel® MAX® 10
ZQSFP0_3V3_LPMODE A11 3.3V QSFP module 0 Low Power signal to Intel® MAX® 10
ZQSFP0_3V3_INT_L E8 3.3V QSFP module 0 interrupt signal to Intel® MAX® 10
ZQSFP0_3V3_MODSEL_L A3 3.3V QSFP module 0 Mode Select signal to Intel® MAX® 10
ZQSFP1_3V3_RESET_L A7 3.3V QSFP module 1 Reset signal to Intel® MAX® 10
ZQSFP1_3V3_MODPRS_L A6 3.3V QSFP module 1 Present signal to Intel® MAX® 10
ZQSFP1_3V3_LPMODE B6 3.3V QSFP module 1 Low Power signal to Intel® MAX® 10
ZQSFP1_3V3_INT_L A4 3.3V QSFP module 1 interrupt signal to Intel® MAX® 10
ZQSFP1_3V3_MODSEL_L B5 3.3V QSFP module 1 Mode Select signal to Intel® MAX® 10
PCIE_RT_JTAG_TCK C10 3.3V PCIe* Root Port JTAG signal
PCIE_RT_JTAG_TDI A8 3.3V PCIe* Root Port JTAG signal
PCIE_RT_JTAG_TMS C9 3.3V PCIe* Root Port JTAG signal
PCIE_RT_JTAG_TDO A9 3.3V PCIe* Root Port JTAG signal
PCIE_RT_JTAG_TRSTn B2 3.3V PCIe* Root Port JTAG signal
PCIE_RT_PERSTn D1 3.3V PCIe* Root Port signal
PCIE_RT_PRSNT2n C2 3.3V PCIe* Rootport signal
PCIE_RT_S10_PERSTn F12 1.8V PCIe* Root Port signal ( Intel® MAX® 10 to FPGA)
PCIE_RT_S10_PRSNT2n E12 1.8V PCIe* Rootport signal ( Intel® MAX® 10 to FPGA)
PCIE_RT_WAKEN B4 3.3V PCIe* Rootport Wake signal
PCIE_EP_JTAG_TCK E3 3.3V PCIe* EndPoint JTAG signal
PCIE_EP_JTAG_TDI F1 3.3V PCIe* EndPoint JTAG signal
PCIE_EP_JTAG_TMS C1 3.3V PCIe* EndPoint JTAG signal
PCIE_EP_JTAG_TDO F4 3.3V PCIe* EndPoint JTAG signal
S10_CVP_CONFDONE E9 1.8V CVP_CONFDONE signal from FPGA to Intel® MAX® 10
S10_CONF_DONE B11 1.8V CONF_DONE signal from FPGA to Intel® MAX® 10
S10_INIT_DONE C12 1.8V INIT_DONE signal from FPGA to Intel® MAX® 10
CPU_RESETn C13 1.8V RESETn signal from Intel® MAX® 10 to FPGA
S10_NCONFIG D9 1.8V N_CONFIG signal from Intel® MAX® 10 to FPGA
SI5341_ENn B13 1.8V Clock enable signal
SI5341_RSTn C11 1.8V Check chip reset
SI5341_FINC A!2 1.8V Clock Frequency increment control
SI5341_FDEC E10 1.8V Clock Frequency decrement control
EXT_JTAG_TDI L3 3.3V External JTAG signal
EXT_JTAG_TCK J1 3.3V External JTAG signal
EXT_JTAG_TMS M2 3.3V External JTAG signal
EXT_JTAG_TDO K2 3.3V External JTAG signal
PWR_MAX10_BYPASSn J2 3.3V Power Intel® MAX® 10 JTAG Bypass input (select by Dip switch SW2-2)
PCIE_RT_BYPASSn M2 3.3V PCIe* Root Port JTAG Bypass input (select by Dip Switch SW2-3)
S10_BYPASSn E4 3.3V FPGA JTAG Bypass input (select by Dip Switch SW2-4)
JTAG_INPUT_SOURCE M3 3.3V JTAG input source selection, SW2-1 select between external JTAG or PCIE EP JTAG
PCIE_EP_3V3_I2C_SDA L2 3.3V I2C bus from PCIE_End Point
PCIE_EP_3V3_I2C_SCL K1 3.3V I2C bus from PCIE_End Point
MAIN_I2C_SCL F8 1.8V Main I2C bus ( Intel® MAX® 10)
MAIN_I2C_SDA B12 1.8V Main I2C bus ( Intel® MAX® 10)
3V3_I2C_EN H3 3.3V This Intel® MAX® 10 signal controls U22 that allows 3V3_I2C bus connect to the Main I2C bus
S10_PMBUS_EN G4 3.3V This Intel® MAX® 10 signal controls U20 that allows CORE_PMBus connect to the S10 SDM I2C bus
MAIN_PMBUS_EN H2 3.3V This Intel® MAX® 10 signal controls U21 that allows CORE_PMBus connect to MAIN I2C bus
PWR_GOOD E1 3.3V Power Good signal from Intel® MAX® 10 Power
Level Two Title