AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

ID 683838
Date 10/12/2020

1.2.3. Generating the Initial HDL in Platform Designer

  1. In the Quartus Prime Pro Edition navigation bar, select Tools > Platform Designer .
  2. In the Platform Designer window, select File > Open > qsys_top.qsys .
  3. In the System View tab, double click on s10_hps to open the HPS Parameters window.
    Figure 2. System Contents Window
  4. Go to Pin Mux and Peripherals > Advanced > Advanced FPGA placement and select the Route to FPGA box for SPIM0 to Yes, then click on Apply Selections.
  5. Double click in the Export column to export the s10_hps.spim0 conduit.
  6. Double click in the Export column to export the s10_hps.spim0_sclk_out conduit.
    Figure 3. Exported Signals
  7. Add a new GPIO soft IP to use as SPI chip select.
  8. Add a new component of type PIO (Parallel I/O) Intel FPGA IP, name it spi_cs_pio and configure it as follows:
    • Width: 1
    • Direction: bidir
    • Enable individual bit setting/clearing: yes
    • Output Port Reset Value: 0x0000000000000001
    Figure 4. PIO Settings
  9. Change the base address of spi_cs_pio.s1 to 0x0001_0000 to avoid conflicts with other IPs.
  10. Connect the spi_cs_pio as follows:

    clk: to clk_100.out_clk

    reset: to rst_in.out_reset

    s1: to s10_hps.h2f_lw_axi_master

    Double click on the spi_cs_pio.external connection to export it and create the conduit spi_cs_pio.spi_cs_pio_external_connection_export.

    Figure 5. PIO Connections
  11. Go to Generate > Show Instantiation Template, and save the template in a file, so you have the new signal names for qsys_top.
  12. Click on the Generate button to generate the system.