AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

ID 683838
Date 10/12/2020
Public

1.2.4. Modifying Top Level File

  1. In the ghrd_s10_top.v, add the top level signals connecting to SPI.
    Note: Only a partial view displayed, below.
    module ghrd_s10_top (
    output wire spi_clk,
    output wire spi_cs,
    output wire spi_mosi,
    input  wire spi_miso,
    
  2. Connect the relevant Platform Designer exported signals to the top level signals:
    Note: Only a partial view displayed, below.
    qsys_top soc_inst (
    .s10_hps_spim0_sclk_out_clk            (spi_clk),
    .spi_cs_pio_external_connection_export (spi_cs),
    .s10_hps_spim0_mosi_o                  (spi_mosi),
    .s10_hps_spim0_miso_i                  (spi_miso),
    .s10_hps_spim0_ss_in_n                 (1'b1),
    

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