AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

ID 683838
Date 10/12/2020
Public
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1.2.5. Adding Pin Assignments for SPIM0

In ghrd_1sx280lu2f50e2vg.qsf, connect the top level signals to the correct pins on the Intel® Stratix® 10 SoC development kit, and set them to 1.8V:
set_location_assignment PIN_BD28 -to spi_clk
set_location_assignment PIN_BF26 -to spi_cs
set_location_assignment PIN_BC28 -to spi_mosi
set_location_assignment PIN_BE27 -to spi_miso
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk -entity\
 ghrd_s10_top
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_cs -entity\
 ghrd_s10_top
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi -entity\
 ghrd_s10_top
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso -entity\
 ghrd_s10_top