AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

ID 683838
Date 10/12/2020
Public

1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

Updated for:
Intel® Quartus® Prime Design Suite 20.3

The Intel® Stratix® 10 SoC device families integrate an Arm* Cortex-A53-based hard processor system (HPS) consisting of processor, peripherals, and memory interface with the FPGA fabric using a high-bandwidth interconnect backbone. The Intel® Stratix® 10 HPS interface provides up to 48 I/O pins to share with multiple peripherals through sets of configurable multiplexers.

This application note describes the steps required to route an HPS peripheral through the FPGA interface using Platform Designer and Intel® Quartus® Prime Pro Edition software version software. A simple design example is included to demonstrate exporting HPS SPIM0 peripheral signals to the FPGA interface using an Intel® Stratix® 10 SoC Development Kit.

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