AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

ID 683838
Date 10/12/2020
Public

1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA

This design example, based on the Golden System Reference Design (GSRD), uses the Intel® Stratix® 10 SoC Development Kit resources to demonstrate the routing of the Intel® Stratix® 10 HPS SPIM0 peripheral signals to the FPGA interface.

Figure 1. High-level Routing Layout of Intel® Stratix® 10 SoC Board Design Example

The following sections, in this document, provide the necessary information to route the HPS peripherals to the FPGA interface.

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