AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

ID 683838
Date 10/12/2020

1.2.6. Hardware Programming File Compilation and Generation

After the Platform Designer system is set up, the top level RTL file is updated, the related signal pin location is assigned and timing constrained, the design can be compiled and the SOF programming file generated.

In the Quartus Prime Pro Edition navigation bar, select Processing > Start Compilation to generate the SOF programming file.