Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 1/29/2024
Document Table of Contents PCIe0 PRS

Table 82.  PCIe0 PRS
Parameter Value Default Value Description

PF0 Enable PRS

On / Off


Enable PF0Page Request Service (PRS) capability.

PF0 Page Request Services Outstanding Capacity

32 bits 0x0000000000000000

This parameter is the upper limit on the number of pages that can be usefully allocated to the Page Request Interface (PRS).