Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 1/29/2024
Document Table of Contents

1.2. Known Issues

The following summarizes known issues in the current IP release:
  1. Multichannel D2H AVST configuration has stability issues when total number of D2H channels configured is greater than 256
  2. Design Example simulation in Intel® Quartus® Prime 23.4 release is failing for BAM+BAS+MCDMA user mode in H-Tile, when SRIOV is enabled.
  3. MCDMA R-Tile Design Example simulations are not supported in Intel® Quartus® Prime 23.4 release, except for PIO using MCDMA Bypass Mode Design Example.
  4. Avalon-ST Source (H2D) interface data can get corrupted, if a Completion timeout event occurs for H2DDM descriptor fetch. This issue happens only if the SOP descriptor is fetched successfully and the EOP descriptor for a channel got missed because of the Completion timeout event.
  5. FLR request is not completed gracefully, when assertion of Soft reset happens during FLR request is still under process.
  6. MCDMA Root Port may drop multi-function Mem Rd Packets targeted to remote device as multi- function enabled End Point.
  7. Few data drops may occur on a channel when a Q_RESET occurs on different channel, which is waiting for a Descriptor Fetch CPL after issuing a hardware instruction.
  8. MCDMA P/F-Tile Design Example [Device-side Packet loopback, Packet Generate/Check and Traffic Generator/Checker] simulations are not supported for Gen3 Hard IP configurations.
  9. MCDMA H/P/F/R-Tile does not support single physical function with one DMA Channel allocated and no SRIOV enabled configuration.
  10. PIO read/write values do not match for certain addresses for PIO bypass mode DE with BAM+BAS or BAM+MCDMA or BAM+BAS+MCDMA modes.
  11. MCDMA P-Tile 1x8 Hard IP mode with Debug Toolkit enabled does not load in system-console for Intel® Stratix® 10 DX Development Kit.
Note: These issues may be addressed in a future release of Intel® Quartus® Prime software.