Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 1/29/2024
Document Table of Contents D2H Descriptor Format (d2hdm_desc)

Table 32.  D2H Descriptor Format
Name Width Description
SRC_ADDR [63:0] 64

Starting local memory address of allocated transmit buffer read by DMA and instruction must be DMWr for DMA operation with MM_mode=1.

Application specific bit indicates whether this command is an Interrupt.

If App_specific_bit=001, MM_mode=0

MM_mode=1: Starting local memory address of allocated transmit buffer read by DMA and instruction must be DMWr for DMA operation.

MM_mode=0: Expectations is to use the DMWr command for WB / MSIx interrupt.

DEST_ADDR [127:64] 64

Destination system address where the DM sends the data to in the host memory.

When MM_mode=0, instruction is DMWr, app_specific_bits=001
  • When app_specific_bits=010, contains the WB address H/L from external DMA’s QCSR
PYLD_CNT [147:128] 20

DMA payload size in bytes. Max 1 MB, with 20’h0 indicating 1 MB

DM_FmtType [155:148] 8

‘h60: DMWr

RSVD [159:156] 1


PFVF [175:160] 16

{VF_ACTIVE, VFNUM[10:0], PF[3:0]}

MM_mode [176:176] 1

MM_mode=0: Only when Write back is intended. It is illegal and behavior is undefined if a DMRd is instructed with MM_Mode=0;

MM_mode=1: Indication to D2H DM to transfer the data to Host side. MM_mode=1 with DMWr command enables reading local FPGA memory and writing to host memory.

App_specific_bits [179:177] 3

Application-specific bits.

An example use case is that the external DMA controller set these bits to generate the Interrupt.

DESC_IDX1 [195:180] 16

Unique Identifier for each descriptor, the same ID will be applied AVST source status signaling (d2hdm_desc_status) returning the status of the data mover completion to DMA controller.

RSVD [196:196] 1


RSVD [212:197] 16


DESC_IDX2 [224:213] 12


Descriptor ID field providing additional provision for descriptor fetch engine to embed information such as channel number, etc. which the completion status on AVST will return unedited for the response completion packet.

If not used, the user external DMA controller is expected to drive this field to zero. The data mover subsystem will treat the descriptor ID field as {DESC_IDX2, DESC_IDX1}.

RSVD [255:225]

31 Reserved
Table 33.  Writeback and MSI-X Format
D2H Data Mover Descriptor Data Bus Write Back MSI-X
d2hdm_desc_data_i [63:0]

64-bits Writeback Data: Write-back Data [63:0]

32-bits Writeback Data: {32'h0, Write-back Data [31:0]}

32-bits MSI-X Data: {32'h0,MSI-X Data [31:0]}

d2hdm_desc datai [127:64]

Write-back Host Address [63:0]

MSI-X Address [63:0]

d2hdm_desc_data_i [147:128]

Payload size in bytes

64-bits Write back Data: 'd8

32-bits Write back Data: 'd4

Payload size in bytes

32-bits MSI-X Data: 'd4

d2hdm_desc_data_i [155:148]

Data Mover Write: 'h60

Data Mover Write: 'h60
d2hdm_desc_data_i [159:156]

Reserved : '0

Reserved: '0
d2hdm_desc_data_i [175:160]

{VF_ACTIVE, VFNUM [10:0], PF[3:0]}

{VF_ACTIVE, VFNUM [10:0], PF[3:0]}
d2hdm_desc_data_i [176:176]

MM_mode : 1'b0

MM_mode: 1'b0

d2hdm_desc_data_i [255:177]

Reserved : '0

Reserved: '0