Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 1/29/2024
Document Table of Contents

4.9. Hard IP Reconfiguration Interface

Table 49.  Hard IP Reconfiguration Interface
Signal Name I/O Description
usr_hip_reconfig_clk_o Output

Use this clock to drive the usr_hip_reconfig interface.

usr_hip_reconfig_rst_n_o Output

Active low Reset w.r.t usr_hip_reconfig_clk_o.

usr_hip_reconfig_readdata_o[7:0] Output read data out
usr_hip_reconfig_readdatavalid_o Output

When asserted, the data on hip_reconfig_readdata[7:0] is


usr_hip_reconfig_write_i Input Write enable
usr_hip_reconfig_read_i Input Read enable

H-Tile, P-Tile and F-Tile: usr_hip_reconfig_address_i[20:0]

R-Tile: usr_hip_reconfig_address_i[31:0]

Input Reconfig register address
usr_hip_reconfig_writedata_i[7:0] Input Write data
usr_hip_reconfig_waitrequest_o Output When asserted, this signal indicates that the IP core is not ready to respond to a request.