Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 1/29/2024
Document Table of Contents

4.14. Precision Time Management (PTM) Interface

The following considerations must be taken into account when implementing the PTM feature with R-Tile MCDMA IP:
  • PTM interface is only supported for Endpoint in Port 0 and 1.
  • PTM accuracy in the common clock scheme is +/-50 ns.
  • PTM accuracy in the separate clock scheme is +/-100 ns.
Table 57.  PTM Interface Signals
Signal Name I/O Description
ptm_context_valid_o Output

When this signal is asserted, it indicates that the value present on the ptm_time bus is valid. Hardware will deassert this bit whenever a PTM dialogue is requested and an update is in progress.

ptm_clk_updated_o Output

This one clock pulse is an indication that the PTM dialogue has completed and the results of that operation have been driven on the ptm_time bus.

ptm_local_clock_o[63:0] Output

This bus contains the calculated master time at t1’ as indicated in the PCIe spec plus any latency to do the calculation and to drive the value to the requester.

ptm_manual_update_i Input

Asserted high for one coreclkout_hip clock when the user application wants to request a PTM handshake to get a snapshot of the latest time.

For detailed information about topic refer to R-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide.