Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/02/2023

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Document Table of Contents Adding Pre-Synthesis or Post-Fit Nodes

To add one or more pre-synthesis or post-fit signals to the Signal Tap Node list for monitoring:
  1. Click either of the following commands to generate the pre-synthesis or post-fit design netlist:
    • Processing > Start > Start Analysis & Elaboration (generates pre-synthesis netlist)
    • Processing > Start > Start Fitter (generates post-fit netlist)
  2. In the Signal Tap logic analyzer, Click Edit > Add Nodes. The Node Finder appears, allowing you to find and add the signals in your design. The following Filter options are available for finding the nodes you want:
    • Signal Tap: pre-synthesis—finds signal names present after design elaboration, but before any synthesis optimizations are done. Signal Tap: pre-synthesis preserved for debug finds presynthesis signals that you mark with the preserve_for_debug pragma, as Preserving Signals for Monitoring and Debugging describes.
    • Signal Tap: post-fitting—finds signal names present after physical synthesis optimizations and place-and-route. Signal Tap: post-fitting preserved for debug finds post-fit signals that you mark with the preserve_for_debug pragma.
  3. In the Node Finder, select one or more nodes that you want to add, and then click the Copy all to Selected Nodes list button.
  4. Click Insert. The nodes are added to the Setup tab signal list in the Signal Tap logic analyzer GUI.
  5. Specify how the logic analyzer uses the signal by enabling or disabling the Data Enable, Trigger Enable, or Storage Enable option for the signal:
    • Trigger Enable—disabling prevents a signal from triggering the analysis, while still showing the signal's captured data.
    • Data Enable—disabling prevent capture of data, while still allowing the signal to trigger.
    Figure 34.  Signal Tap Node List Options for Data Enable and Trigger Enable
  6. Define trigger conditions for the Signal Tap nodes, as Defining Trigger Conditions describes.

The number of channels available in the Signal Tap window waveform display is directly proportional to the number of logic elements (LEs) or adaptive logic modules (ALMs) in the device. Therefore, there is a physical restriction on the number of channels that are available for monitoring. Signals shown in blue text are post-fit node names. Signals shown in black text are pre-synthesis node names.

After successful Analysis and Elaboration, invalid signals appear in red. Unless you are certain that these signals are valid, remove them from the .stp file for correct operation. The Signal Tap Status Indicator also indicates if an invalid node name exists in the .stp file.

You can monitor signals only if a routing resource (row or column interconnects) exists to route the connection to the Signal Tap instance. For example, you cannot monitor signals that exist in the I/O element (IOE), because there are no direct routing resources from the signal in an IOE to a core logic element. For input pins, you can monitor the signal that is driving a logic array block (LAB) from an IOE, or, for output pins, you can monitor the signal from the LAB that is driving an IOE.


The Intel® Quartus® Prime Pro Edition software uses only the instance name, and not the entity name, in the form of:


not a_entity:a|b_entity:b|c_entity:c