Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/02/2023

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7.6. Design Example: Dynamic PLL Reconfiguration

The In-System Sources and Probes Editor can help you create a virtual front panel during the prototyping phase of your design. You can create relatively simple, high functioning designs of in a short amount of time. The following PLL reconfiguration example demonstrates how to use the In-System Sources and Probes Editor to provide a GUI to dynamically reconfigure a Stratix® PLL.

Stratix® PLLs allow you to dynamically update PLL coefficients during run time. Each enhanced PLL within the Stratix® device contains a register chain that allows you to modify the pre-scale counters (m and n values), output divide counters, and delay counters. In addition, the ALTPLL_RECONFIG IP core provides an easy interface to access the register chain counters. The ALTPLL_RECONFIG IP core provides a cache that contains all modifiable PLL parameters. After you update all the PLL parameters in the cache, the ALTPLL_RECONFIG IP core drives the PLL register chain to update the PLL with the updated parameters. The figure shows a Stratix® -enhanced PLL with reconfigurable coefficients.

Figure 108.  Stratix® -Enhanced PLL with Reconfigurable Coefficients

The following design example uses an ALTSOURCE_PROBE instance to update the PLL parameters in the ALTPLL_RECONFIG IP core cache. The ALTPLL_RECONFIG IP core connects to an enhanced PLL in a Stratix® FPGA to drive the register chain containing the PLL reconfigurable coefficients. This design example uses a Tcl/Tk script to generate a GUI where you can enter in new m and n values for the enhanced PLL. The Tcl script extracts the m and n values from the GUI, shifts the values out to the ALTSOURCE_PROBE instances to update the values in the ALTPLL_RECONFIG IP core cache, and asserts the reconfiguration signal on the ALTPLL_RECONFIG IP core. The reconfiguration signal on the ALTPLL_RECONFIG IP core starts the register chain transaction to update all PLL reconfigurable coefficients.
Figure 109. Block Diagram of Dynamic PLL Reconfiguration Design Example

This design example was created using a Nios® II Development Kit, Stratix® Edition. The file contains all the necessary files for running this design example, including the following:

  • Readme.txt—A text file that describes the files contained in the design example and provides instructions about running the Tk GUI shown in the figure below.
  • Interactive_Reconfig.qar—The archived Intel® Quartus® Prime project for this design example.
    Figure 110. Interactive PLL Reconfiguration GUI Created with Tk and In-System Sources and Probes Tcl Package