Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/02/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1.1. System Debugging Tools Comparison

Table 1.  System Debugging Tools Portfolio
Tool Description Typical Usage
System Console and Debugging Toolkits
  • Provides real-time in-system debugging capabilities using available debugging toolkits.
  • Allows you to read from and write to memory mapped components in a system without a processor or additional software.
  • Communicates with hardware modules in a design through a Tcl interpreter.
  • Allows you to take advantage of all the features of the Tcl scripting language.
  • Supports JTAG and TCP/IP connectivity.
  • Perform system-level debugging.
  • Debug or optimize signal integrity of a board layout even before finishing the design.
  • Debug external memory interfaces.
  • Debug an Ethernet Intel FPGA IP interface in real time.
  • Debug a PCI Express* link at the Physical, Data Link, and Transaction layers.
  • Debug and optimize high-speed serial links in your board design.
Signal Tap logic analyzer
  • Uses FPGA resources.
  • Captures data continuously from the signals you specify while the logic analyzer is running. To capture and store only specific signal data, you specify conditions that trigger the start or stop of data capture. A trigger activates when the trigger conditions are met, stopping analysis and displaying the data
You have spare on-chip memory and you want functional verification of a design running in hardware.
Signal Probe Incrementally routes internal signals to I/O pins while preserving results from the last place-and-routed design. You have spare I/O pins and you want to check the operation of a small set of control pins using either an external logic analyzer or an oscilloscope.
Logic Analyzer Interface (LAI)
  • Multiplexes a larger set of signals to a smaller number of spare I/O pins.
  • Allows you to select which signals switch onto the I/O pins over a JTAG connection.
You have limited on-chip memory and a large set of internal data buses to verify using an external logic analyzer. Logic analyzer vendors, such as Tektronics* and Agilent*, provide integration with the tool to improve usability.
In-System Sources and Probes Provides an easy way to drive and sample logic values to and from internal nodes using the JTAG interface. Provides real-time slow sampling capability. You want to prototype the FPGA design using a front panel with virtual buttons.
In-System Memory Content Editor Displays and allows you to edit on-chip memory.

You want to view and edit the contents of on-chip memory that is not connected to a Nios® II processor.

You can also use the tool when you do not want to have a Nios® II debug core in your system.

Virtual JTAG Interface Allows you to communicate with the JTAG interface so that you can develop custom applications. You want to communicate with custom signals in your design.

Refer to the following for more information about launching and using the available debugging toolkits: