EPCQ-A Serial Configuration Device Datasheet

ID 683818
Date 10/01/2019
Public
Document Table of Contents

1.7.1. Timing Requirements

When the active low chip select (nCS) signal is driven low, shift in the operation code into the EPCQ-A device using theDATA0 pin. Each operation code bit is latched into the EPCQ-A device at rising edges of the DCLK signal.

While executing an operation, shift in the desired operation code, followed by the address or data bytes. See related information for more information about the address and data bytes. The device must drive the nCS pin high after the last bit of the operation sequence is shifted in.

For read operations, the data read is shifted out on the DATA[3:0] pins. You can drive the nCS pin high when any bit of the data is shifted out.

For write and erase operations, drive the nCS pin high at a byte boundary, that is in a multiple of eight clock pulses. Otherwise, the operation is rejected and not executed.

All attempts to access the memory contents while a write or erase cycle is in progress are rejected, and the write or erase cycle continues unaffected.

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