EPCQ-A Serial Configuration Device Datasheet

ID 683818
Date 10/01/2019
Public
Document Table of Contents

1.9.14. Read SFDP Register Operation (5Ah)

The 256-byte SFDP register contains information about device configurations, available operations and other features.

The Read SFDP Register operation is compatible with the JEDEC SFDP standard, JESD216A. For SFDP register values and descriptions, please refer to Appendix: SFDP Register Definitions.

Figure 19. Read SFDP Register Operation Timing Diagram

Initiate the Read SFDP operation by driving the nCS pin low and shifting the operations code followed by a 3-byte address into the DATA0 pin. The 3-byte address content:

  • A[23..8] = 0
  • A[7..0] = Defines the starting byte address for the 256-byte SFDP register

Eight dummy clock cycles are required before the SFDP register contents are shifted out on the falling edge of the 40th DCLK with the most significant bit (MSB) first.

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