EPCQ-A Serial Configuration Device Datasheet

ID 683818
Date 10/01/2019
Public
Document Table of Contents

1.9. Summary of Operation Codes

Operation Operation Code 7 Address Bytes Dummy Clock Cycles Data Bytes DCLK fMAX (MHz)
Read status 05h 0 0 1 to infinite 8 100
Read bytes 03h 3 0 1 to infinite8 50
Read device identification 9Fh 0 16 1 100
Read silicon identification ABh 0 24 1 100
Fast read 0Bh 3 8 1 to infinite8 100
Extended dual input fast read BBh 3 4 1 to infinite8 100
Extended quad input fast read 9 EBh 3 6 1 to infinite8 100
Write enable 06h 0 0 0 100
Write disable 04h 0 0 0 100
Write status 01h 0 0 1 100
Write bytes 02h 3 0 1 to 256 10 100
Quad input fast write bytes9 32h 3 0 1 to 25610 100
Erase bulk C7h 0 0 0 100
Erase sector D8h 3 0 0 100
Erase subsector 20h 3 0 0 100
Read SFDP register9 5Ah 3 8 1 to 256 100
7 List MSB first and LSB last.
8 The status register or data is read out at least once and is continuously read out until the nCS pin is driven high.
9 This operation is not applicable for EPCQ4A.
10 A write bytes operation requires at least one data byte. If more than 256 bytes are sent to the device, only the last 256 bytes are written to the memory.

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