EPCQ-A Serial Configuration Device Datasheet

ID 683818
Date 10/01/2019
Document Table of Contents

1.8. Status Register

Table 16.  Status Register Bits
Bit R/W Default Value Name Value Description
7 R/W 0 5 Reserved
6 R/W 05 Reserved
5 R/W 0 TB (Top/Bottom Bit)
  • 1=Protected area starts from the bottom of the memory array.
  • 0=Protected area starts from the top of the memory array.
Determine that the protected area starts from the top or bottom of the memory array.
4 R/W 0 BP2 6 Table 17 through Table 21 list the protected area with reference to the block protect bits. Determine the area of the memory protected from being written or erased unintentionally.
3 R/W 0 BP16
2 R/W 0 BP06
1 R 0 WEL (Write Enable Latch Bit)
  • 1=Allows the following operation to run:
    • Write Bytes
    • Write Status Register
    • Erase Bulk
    • Erase Sector
  • 0=Rejects the above mentioned operations.
Allows or rejects certain operation to run.
0 R 0 WIP (Write in Progress Bit)
  • 1=One of the following operation is in progress:
    • Write Status Register
    • Write Bytes
    • Erase
  • 0=no write or erase cycle in progress
Indicates if there is a command in progress.
5 Do not program these bits to 1.
6 The erase bulk and erase die operation is only available when all the block protect bits are set to 0. When any of the block protect bits are set to 1, the relevant area is protected from being written by a write bytes operation or erased by an erase sector operation.

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