EPCQ-A Serial Configuration Device Datasheet

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ID 683818
Date 10/01/2019
Public
Document Table of Contents

1.9.8. Write Disable Operation (04h)

The write disable operation resets the write enable latch bit in the status register. To prevent the memory from being written unintentionally, the write enable latch bit is automatically reset when implementing the write disable operation, and under the following conditions:

  • Power up
  • Write bytes operation completion
  • Write status operation completion
  • Erase bulk operation completion
  • Erase sector operation completion
  • Quad input fast write bytes operation completion
Figure 13. Write Disable Operation Timing Diagram


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