EPCQ-A Serial Configuration Device Datasheet

ID 683818
Date 10/01/2019
Public
Document Table of Contents

1.11.2. Read Operation Timing

Figure 21. Read Operation Timing Diagram
Table 25.  Read Operation Parameters
Symbol Parameter Min Max Unit
fRCLK Read clock frequency (from the FPGA or embedded processor) for read bytes operations 50 MHz
Fast read clock frequency (from the FPGA or embedded processor) for fast read bytes operation 100 MHz
tCH DCLK high time for EPCQ4A. 4 or 6 14 ns
DCLK high time for EPCQ16A, EPCQ32A, EPCQ64A, and EPCQ128A. 3.4 or 9 15 ns
tCL DCLK low time for EPCQ4A. 4 or 614 ns
DCLK low time for EPCQ16A, EPCQ32A, EPCQ64A, and EPCQ128A. 3.4 or 915   ns
tODIS Output disable time after read 7 ns
tCLQV Clock low to output valid for EPCQ4A. 8 ns
Clock low to output valid for EPCQ16A, EPCQ32A, EPCQ64A, and EPCQ128A. 6
tCLQX Output hold time for EPCQ4A. 0 ns
Output hold time for EPCQ16A, EPCQ32A, EPCQ64A, and EPCQ128A. 1.5
14 4 ns for fast read and 6 ns for read.
15 3.4 ns for fast read and 9 ns for read.

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