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2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages
1.2 V VCCIO_PIO
If you use a 1.2 V VCCIO_PIO, you can implement singled-ended non-voltage referenced and voltage-referenced I/O standards. The 1.2 V buffer also supports differential voltage-referenced I/O and true differential input standards.
You can implement a mix of both voltage-referenced and non-voltage referenced I/O, and true differential input standards within the I/O bank.
1.5 V VCCIO_PIO
If you use a 1.5 V VCCIO_PIO voltage, you can implement only the True Differential Signaling I/O standard. The buffer can interface with upstream or downstream devices that are compatible with the F-Series and I-Series FPGAs electrical specifications.
Analyze the electrical specification requirement to implement your true differential receiver.
Implement DC coupling if the signal swing and offset voltage requirement are within the F-Series and I-Series True Differential Signaling standard specification. Otherwise, implement AC coupling and external bias circuitry.
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