Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series

ID 683780
Date 2/20/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.5.17. 1.2 V I/O Interface Voltage Level Compatibility

Evaluate the electrical signal level compatibility between F-Series and I-Series 1.2 V output and the downstream device. Ensure that the VOH and VOL voltages of the 1.2 V output buffer conform to the VIH and VIL specifications of the receiving buffer of the downstream device.

1.2 V LVCMOS I/O Standard Voltage Swing Calculation

If you use the 1.2 V LVCMOS I/O standard, the output signal swings from 0 V to 1.2 V on a lossless transmission line with no external pull-up or pull-down component. Ensure that the VIH or VIL tolerance of the downstream connecting device can meet those conditions.

1.2 V Voltage-Referenced I/O Standards Voltage Swing Calculation

If you use the 1.2 V voltage-referenced I/O standards, the output signal swing has a dependency on the external board termination or the internal termination of the receiver.

Figure 20. Termination Setup Using 40 Ω RS OCT Driver with On-Board 50 Ω Pull-Up Resistor to VCCIO_PIO/2 This figure shows an example termination setup and its equivalent circuit.
Figure 21. Equivalent Circuit of the Example with Output Buffer Driving HIGHWhen the output buffer is driving HIGH, the pin voltage is 0.93 V based on voltage divider rule.
Figure 22. Equivalent Circuit of the Example with Output Buffer Driving LOWWhen the output buffer is driving LOW, the pin voltage is 0.27 V based on the voltage divider rule.