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1. Intel® Agilex™ 7 F-Series and I-Series General-Purpose I/O Overview 2. Intel® Agilex™ 7 F-Series and I-Series GPIO Banks 3. Intel® Agilex™ 7 F-Series and I-Series HPS I/O Banks 4. Intel® Agilex™ 7 F-Series and I-Series SDM I/O Banks 5. Intel® Agilex™ 7 F-Series and I-Series I/O Troubleshooting Guidelines 6. Intel® Agilex™ 7 F-Series and I-Series General-Purpose I/O IPs 7. Programmable I/O Features Description 8. Documentation Related to the Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series 9. Document Revision History for the Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
2.5.1. VREF Sources and VREF Pins 2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages 2.5.3. OCT Calibration Block Requirement 2.5.4. I/O Pins Placement Requirements 2.5.5. I/O Standard Selection and I/O Bank Supply Compatibility Check 2.5.6. Simultaneous Switching Noise 2.5.7. Special Pins Requirement 2.5.8. External Memory Interface Pin Placement Requirements 2.5.9. HPS Shared I/O Requirements 2.5.10. Clocking Requirements 2.5.11. SDM Shared I/O Requirements 2.5.12. Unused Pins 2.5.13. Voltage Setting for Unused GPIO Banks 2.5.14. GPIO Pins During Power Sequencing 2.5.15. Drive Strength Requirement for GPIO Input Pins 2.5.16. Maximum DC Current Restrictions 2.5.17. 1.2 V I/O Interface Voltage Level Compatibility 2.5.18. GPIO Pins for the Avalon® Streaming Interface Configuration Scheme 2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane
6.1.1. Release Information for GPIO Intel® FPGA IP 6.1.2. Generating the GPIO Intel® FPGA IP 6.1.3. GPIO Intel® FPGA IP Parameter Settings 6.1.4. GPIO Intel® FPGA IP Interface Signals 6.1.5. GPIO Intel® FPGA IP Architecture 6.1.6. Verifying Resource Utilization and Design Performance 6.1.7. GPIO Intel® FPGA IP Timing 6.1.8. GPIO Intel® FPGA IP Design Examples
8. Documentation Related to the Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
2.2. GPIO Features
The I/O bank within the GPIO interface supports differential and single-ended I/O standards. The GPIO bank has true differential I/O buffer pairs using the True Differential Signaling I/O standard—compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL I/O standards. One true differential buffer pair forms a true differential channel.
- If you use SERDES, half of the true differential buffers support dedicated transmitter channels and the other half support dedicated true receiver channels. Refer to the device pin-out files for locations of the dedicated receiver and transmitter channels.
- If you do not use SERDES, you can configure any of the true differential buffers as transmitter or receiver channels. Each I/O lane support up to six transmitter and three receiver channels.
- The differential voltage referenced output pins are not true differential output pins. The differential voltage referenced I/O standards use two single-ended output pins where one of the output pins is inverted.
Power Pins for the I/O Buffers
The VCCIO_PIO and VCCPT pins power the I/O buffers located in the I/O bank within the GPIO interface.
I/O Buffer Features
- Single-ended non-voltage referenced and voltage-referenced I/O standards
- Differential voltage-referenced I/O standards
- True differential transmitters and receivers
- Serializer/deserializer (SERDES)
- Programmable slew rate
- Programmable bus-hold
- Programmable weak pull-up resistor
- Programmable differential output voltage (VOD) for true differential output buffers
- Programmable open-drain output
- On-chip series termination (RS OCT) with and without calibration
- On-chip parallel termination (RT OCT)
- On-chip differential termination (RD OCT)
- Dynamic on-chip parallel termination
- Internally generated VREF with DDR4 calibration
- Programmable pre-emphasis for true differential output buffer
- Programmable de-emphasis for voltage-referenced I/O standards
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