Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series

ID 683780
Date 2/20/2023
Public

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Document Table of Contents

6.1.5.1. GPIO Intel® FPGA IP Data Paths

Figure 33.  High-Level View of Single-Ended GPIO


Table 50.   GPIO IP Data Path Modes
Data Path Register Mode
Bypass Simple Register DDR I/O
Full-Rate Half-Rate
Input Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data.
Output Data goes from the core straight to the delay element, bypassing all DDIOs. The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data.
Bidirectional The output buffer drives both an output pin and an input buffer. The full-rate DDIO operates as a simple register. The output buffer drives both an output pin and an input buffer. The full-rate DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops.

If you use asynchronous clear and preset signals, all DDIOs share these same signals.

Half-rate and full-rate DDIOs connect to separate clocks. When you use half-rate and full-rate DDIOs, the full-rate clock must run at twice the half-rate frequency. You can use different phase relationships to meet timing requirements.